Boots – shoes – and leggings
Patent
1997-02-11
1999-04-27
Teska, Kevin J.
Boots, shoes, and leggings
364490, G06F 1750
Patent
active
058985972
ABSTRACT:
A method for planning floor allocation of an integrated circuit to each function is disclosed. To provide enough core space to each of the functions and to meet some cost functions such as space utilization requirement of each of the functions, the disclosed method divides the core space to a grid of elementary regions. Then, pieces of the core space are defined and the pieces containing the borders and the overlapping areas of the functions are identified. Then, the identified pieces are used shift the allocated capacities of the functions as to shift excess capacity or core space from the functions with excess capacity to the functions with a shortage of capacity.
REFERENCES:
patent: 5491641 (1996-02-01), Scepanovic et al.
patent: 5495419 (1996-02-01), Rostoker et al.
patent: 5557533 (1996-09-01), Koford et al.
patent: 5568322 (1996-10-01), Azami et al.
patent: 5568636 (1996-10-01), Koford
patent: 5578840 (1996-11-01), Scepanovic et al.
patent: 5615128 (1997-03-01), Scepanovic et al.
patent: 5636125 (1997-06-01), Rostoker et al.
patent: 5638293 (1997-06-01), Scepanovic et al.
patent: 5640327 (1997-06-01), Ting
patent: 5661663 (1997-08-01), Scepanovic et al.
patent: 5682322 (1997-10-01), Boyle et al.
patent: 5699265 (1997-12-01), Scepanovic et al.
patent: 5712793 (1998-01-01), Scepanovic et al.
patent: 5742510 (1998-04-01), Rostoker et al.
patent: 5745363 (1998-04-01), Rostoker et al.
patent: 5757657 (1998-05-01), Hathaway et al.
Schulz ("Hierarchical physical design system", IEEE Comput. Soc. Press, Proceedings on VLSI and Computer Peripherals: VLSI and Microelectonic Applications in Intelligent Peripherals and their Interconnection Networks, May 8, 1989, pp. 5/20-24).
Wu et al. ("Glue-logic partitioning for floorplans with a rectilinear datapath", IEEE Comput. Soc. Press, Proceedings of the European Conference on Design Automation, Feb. 25, 1991, pp. 162-166).
Andreev Alexander E.
Pavisic Ivan
Scepanovic Ranko
Kik Phallaka
LSI Logic Corporation
Teska Kevin J.
LandOfFree
Integrated circuit floor plan optimization system does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Integrated circuit floor plan optimization system, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Integrated circuit floor plan optimization system will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-689500