Static information storage and retrieval – Read/write circuit – Differential sensing
Reexamination Certificate
1999-07-12
2001-02-13
Elms, Richard (Department: 2824)
Static information storage and retrieval
Read/write circuit
Differential sensing
C365S205000
Reexamination Certificate
active
06188624
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to integrated circuits, and more particularly to memory sensing circuits having low latency or delay.
Memory devices are integral to a computer system and to many electronic circuits. Continuous improvements in the operating speed and computing power of a central processing unit (CPU) enable operation of an ever-greater variety of applications, many of which require faster and larger memories. Larger memories can be obtained by shrinking the geometry of the memory cells and the data/control lines within the memory devices. Faster operating speed can be obtained by reducing the charge and discharge times of parasitic capacitance on internal data lines and by improving the data-clocking scheme within the memory devices.
Conventionally, a memory access to retrieve a data bit is performed by: (1) activating a row control line (e.g., a row select line or a word line) for the data bit; (2) waiting for the charge that is stored in a memory cell corresponding to the data bit to generate a voltage on a sense line; (3) sensing the charged voltage on the sense line to determine the value of the data bit; (4) activating a column select line; (5) providing the detected bit value to a data line; and (6) buffering and providing the data bit to an input/output (I/O) pin of the memory device. Conventionally, these steps are performed in sequential order for an accessed data bit. These steps define the access time of the memory device (i.e., to read a data bit), which in turn determines the data transfer rate.
For a dynamic random access memory (DRAM), a memory cell is typically implemented with a small capacitor coupled to a switch. When the memory cell is selected (by activating the switch) the capacitor is coupled to the sense line and shares charge with the parasitic capacitor on the sense line. Since the memory cell capacitance is typically much smaller than the parasitic capacitance, the voltage on the sense line only moves a small amount as a result of the charge sharing. One or more amplifiers are then used to amplify and buffer the voltage on the sense line to allow for accurate detection of the voltage, and thus the value stored in the memory cell. After sensing is completed, the amplifiers are also used to recharge the capacitor to it proper logic state (i.e., its previous state before the read cycle).
For a densely integrated memory device, a large number of memory cells are implemented on one device and many memory cells are coupled to each sense line. As a result, the memory cell capacitor is typically small and the parasitic capacitance on the sense line can be large (relatively). These characteristics result in a longer charge time for the sense line, which can correspond to a longer memory read cycle and a slower data access rate.
As can be seen, circuits that can improve the charge time of the sense line and the detection of the voltage on the sense line are highly desirable.
SUMMARY OF THE INVENTION
The invention provides memory sensing circuits having low latency or delay. In accordance with one aspect of the invention, low latency is achieved, in part, by utilizing multiple amplifiers in the sense amplifier circuit. Each amplifier detects and amplifies a differential voltage on a pair of lines used for sensing a logic state of a memory cell. The use of multiple amplifiers improves the response times of the lines, which can allow for an earlier detection of the voltages on the lines, a shorter memory access cycle, and an improved data transfer rate. In accordance with another aspect of the invention, a set of isolation switches and a latch are provided for the sense amplifier circuit. The latch “captures” the voltages on the lines after the voltages have exceeded a set of thresholds. The latch then provides the captured value to subsequent circuitry at the same time that the lines are “deactivated” (i.e., equalized or precharged to a midscale voltage).
An embodiment of the invention provides a sense amplifier circuit for sensing a logic state of a memory cell. The sense amplifier circuit includes an isolation circuit, a first amplifier, a second amplifier, and a third amplifier. The isolation circuit couples between a first pair of lines and a second pair of lines. The first pair of lines can be the sense amplifier lines and the second pair of lines can be the bit lines. The memory cell is operatively coupled to at least one of the lines in the second pair and shares charge, when selected, with the line(s) to which it couples. Each of the first, second, and third amplifiers couples between one of the pairs of lines and is configured to detect and amplify a voltage difference between the lines to which it couples. In a specific embodiment, the first amplifier is a N-channel amplifier, the second amplifier is a P-channel amplifier, and the third amplifier can be either a N-channel or a P-channel amplifier. The amplifiers can be enabled in a manner to provide improved response time for the lines.
The sense amplifier circuit can further include additional amplifiers (i.e., N-channel or P-channel, or both) that can couple to either the first or second pair of lines, or both, and at various locations along the lines. The additional amplifiers further amplify the voltage difference between the lines. The sense amplifier circuit can also include an equalization circuit coupled between the second pair of lines.
Another embodiment of the invention provides a sense amplifier circuit for sensing a logic state of a memory cell. The sense amplifier circuit includes an isolation circuit, a first amplifier, a second amplifier, a first set of switches, and a latch. The isolation circuit couples between a pair of sense amplifier lines and a pair of bit lines. The memory cell is coupled to at least one of the bit lines and shares charge, when selected, with the line(s) to which it couples. Each of the first and second amplifiers couples between a pair of lines and is configured to detect and amplify a differential voltage on the lines to which it couples. The first set of switches couples between the pair of sense amplifier lines and a pair of data lines. The latch couples between the data lines and is configured to latch a differential voltage on the data lines. The sense amplifier circuit can further include any combination of the features described above.
Yet another embodiment of the invention provides a memory device that includes a row decoder, a column decoder, a memory aray, and a sense amplifier. The row decoder is configured to receive address information and generate a first set of control signals. The column decoder is configured to receive address information and generate a second set of control signals. The memory array couples to the row and column decoders and is configured to provide a data value in response to the first and second sets of control signals. The sense amplifier couples to the memory array and is configured to receive and condition the data value and provide a data bit. The memory device can further include an output circuit and a timing circuit. The output circuit couples to the sense amplifier and is configured to receive the data bit and provide an output bit. The timing circuit couples to the sense amplifier and is configured to provide a set of control signals for the sense amplifier.
The sense amplifier includes an isolation circuit, a first amplifier, a second amplifier, and a third amplifier. The isolation circuit couples between a pair of sense amplifier lines and a pair of bit lines. The data value is provided to at least one of the bit lines. Each of the first, second, and third amplifiers couples between a pair of lines and is configured to detect and amplify a differential voltage on the lines to which it couples. Again, the sense amplifier circuit can further include any combination of the features described above.
The foregoing, together with other aspects of this invention, will become more apparent when referring to the following specification, claims, and accompanying drawings.
Dinh & Associates
Elms Richard
Nguyen Hien
Winbond Electronics Corporation
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