Low latency input-output interface

Details Low latency input-output interface Low latency input-output interface

2000-01-19

2002-10-08

Gaffin, Jeffrey (Department: 2782)

Electrical computers and digital data processing systems: input/

Input/output data processing

Data transfer specifying

C710S033000, C710S022000, C710S027000, C710S305000, C710S306000, C710S307000, C710S308000, C710S311000, C710S312000

Reexamination Certificate

active

06463483

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to control of device buses in processor systems.
BACKGROUND OF THE INVENTION
In microprocessor systems, it is common to interconnect the microprocessor and memory subsystems by way of a parallel local bus. At the current state of the art, a 64-bit local bus is common. In order to make connections between the microprocessor/memory arrangement and the outside world, a “north bridge” interfaces the local bus to an industry-standard bus, such as a PCI bus. The PCI bus allows attachment of standard cards to the system, for purposes such as video and audio interface, printers, scanners, and the like. In addition to standard cards, it may be desirable to provide an interface to other devices, such as programmable timers, additional memory, interrupt controllers, and the like, which do not adhere to any particular standard. These additional devices are ordinarily coupled to a “device” bus, which is interconnected with the PCI bus by way of a “south bridge.” These prior-art systems are widely used and successful.
However, it has been noticed that for some applications, the data throughput is less than desired.
SUMMARY OF THE INVENTION
An interface arrangement according to the invention is for attaching peripheral devices on a device bus to a microprocessor 2
N
-bit local interface bus, where the local interface bus is associated with a north bridge for interfacing a PCI bus to the local interface bus, and may also be associated with a south bridge for interfacing the device bus to the PCI bus. The interface arrangement includes a transfer multiplexer/demultiplexer having a 2
N
-bit parallel first port coupled to the local interface 2
N
-bit bit bus for receiving 2
N
-bit data, and for also receiving transfer size information relating to the 2
N
-bit data. The transfer multiplexer/demultiplexer also includes a parallel second port having no more than 2
N−1
-bits, and further includes a transfer control input port for transferring data between the first and second ports in a time-division multiplex manner under the control of a transfer initiate signal applied to the transfer control input port, a burst count signal, a data direction signal, and a device port size signal. A local bus address decoder is coupled to the local interface bus, for receiving the local address from the microprocessor by way of the local interface bus, and for decoding the local address to determine if the transfer is to/from a device which is attached to the device bus, and if the local address provides access to such a device coupled to the device bus, signalling, by way of the local interface bus, to the microprocessor that the local bus address decoder is assuming control of the transfer associated with the local address, and, if the local bus address decoder is handling the transfer, further decoding the local address to determine the accessed width of the port of the device, to thereby produce the device port size signals. The interface arrangement further includes a transfer size decoder coupled to the local interface bus, for receiving transfer size information relating to the transfer, and also coupled to the local bus address decoder for receiving the port size signals. The transfer size decoder generates a maximum burst count value in response to the quotient of the transfer size divided by the port size, and also generates a step value by addressing a look-up table with the port size, to access prestored values in the look-up table. The prestored values of step size are equivalent to the byte width of the addressed device port. A burst counter is coupled to the transfer control port of the transfer multiplexer/demultiplexer, and to the local interface bus for receiving the local addresses, to the transfer multiplexer/demultiplexer, and is also coupled to the transfer size decoder, for receiving the maximum burst count and the accessed one of the prestored step values. The burst counter performs the following steps:
(a) loading or latching the three least-significant bits of the local addresses into a counter;
(b) following the loading step, transferring the three bits contained in the counter, in parallel, together with the remaining most-significant bits of the local address, also in parallel, to the device bus;
(c) following the transfer of the three bits and the most-significant bits to the device, generating the transfer initiation command for application to the transfer multiplexer/demultiplexer;
(d) after generation of the transfer initiation command, incrementing the counter by the value of the accessed one of the prestored step values; and
(e) repeatedly generating another transfer initiation command and again incrementing the counter, for one less than the number of times specified by the maximum burst count.
The interface arrangement also includes a local microprocessor controller or interface coupled to the local bus, for receiving at least local read and write strobes. The local microprocessor controller also includes a transfer complete strobe signal input port. The local microprocessor controller decodes the read and write strobes to generate a data direction signals representing the direction of data flow through the interface arrangement, and also generates, on the local interface bus, a local acknowledge signal representing completion of data transfer. The interface arrangement further includes a device interface controller coupled to the device bus for receiving device transfer acknowledge signals, coupled to the local microprocessor controller for receiving the data direction signals, and also coupled to the burst counter for receiving the transfer initiate signals. The device interface controller drives the device bus with device control signals in response to the direction control and transfer initiate signals, and produces the transfer complete signals in response to the device transfer acknowledge signals.


REFERENCES:
patent: 5191653 (1993-03-01), Banks et al.
patent: 5450551 (1995-09-01), Amini et al.
patent: 6353867 (2002-03-01), Qureshi et al.
patent: 6393500 (2002-05-01), Thekkath

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