Low latency bridging between high speed bus networks

Details Low latency bridging between high speed bus networks Low latency bridging between high speed bus networks

1998-05-15

2000-07-18

Etienne, Ario

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710129, 710 52, 710 46, 364239, 3642411, G06F 1338

Patent

active

060921404

ABSTRACT:
A network bridge includes a processor, a common memory, a first interface to a first network and a second interface to a second network. Upon the first interface receiving a first request to transfer data from a device on the first network, the processor seeds a portion of a first buffer within the first common memory with a predetermined polling pattern. The processor polls the portion of the first buffer to determine when data has arrived into the first buffer. When the processor determines that data has arrived into the first buffer, the processor authorizes the second interface to set up a write process with a device on the second network.

REFERENCES:
patent: 5377184 (1994-12-01), Beal et al.
patent: 5448701 (1995-09-01), Metz, Jr. et al.
patent: 5732094 (1998-03-01), Petersen et al.
patent: 5809339 (1998-09-01), Howkins et al.

Affiliated with

Also associated with

Rating

Low latency bridging between high speed bus networks does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low latency bridging between high speed bus networks, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low latency bridging between high speed bus networks will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2048674