Low-K sub spacer pocket formation for gate capacitance...

Details Low-K sub spacer pocket formation for gate capacitance... Low-K sub spacer pocket formation for gate capacitance...

1999-07-13

2002-02-26

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S372000, C257S900000, C257S369000, C438S595000

Reexamination Certificate

active

06351013

ABSTRACT:

TECHNICAL FIELD
The present invention relates to a semiconductor device and a method of manufacturing a semiconductor device with reduced capacitance between the gate electrode and the source/drain regions. The present invention is particularly applicable in manufacturing high density CMOS semiconductor devices with design features of 0.25 microns and under.
BACKGROUND ART
The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
Conventional semiconductor devices typically comprise a semiconductor substrate, normally doped monocrystalline silicon, and a plurality of interleaved dielectric and conductive layers formed thereon. In a conventional semiconductor device
100
illustrated in
FIG. 1
, p-type substrate
1
is provided with field oxide
2
for isolating an active region comprising N+ source/drain regions
3
, and a gate electrode
4
, typically of doped polysilicon, above the semiconductor substrate with gate oxide
5
therebetween. Interlayer dielectric layer
6
, typically silicon dioxide, is then deposited thereover and openings formed by conventional photolithographic and etching techniques. The openings are filled with conductive material to establish electrical contact between subsequently deposited conductive layer
8
, typically aluminum or an aluminum-base alloy, and source/drain regions
3
through contacts
7
, and to transistor gate electrode
4
. Dielectric layer
9
, typically silicon dioxide, is deposited on conductive layer
8
, and another conductive layer
10
, typically aluminum or an aluminum-base alloy, formed on dielectric layer
9
and electrically connected to conductive layer
8
through vias
11
.
With continued reference to
FIG. 1
, conductive layer
10
is the uppermost conductive layer and, hence, constitutes the wire bonding layer. Dielectric layer
12
, also typically silicon dioxide, is deposited, and a protective dielectric scratch resistant topside layer
13
deposited thereon. Protective dielectric layer
13
typically comprises a nitride layer, such as silicon nitride (Si
3
N
4
). Alternatively, protective dielectric layer
13
may comprise a dual topcoat comprising a nitride layer on an oxide layer. The protective dielectric layer
13
provides scratch protection to the semiconductor device and protection against moisture and impurity contamination during subsequent processing. After deposition of protective dielectric layer
13
, conventional photolithographic etching techniques are employed to form an opening to expose wire bonding layer
10
for external connection by means of bonding pad
14
and electrically conductive wires
15
or an external connection electrode (not shown).
Although only two conductive layers
8
and
10
are depicted in
FIG. 1
for illustrative convenience, conventional semiconductor devices are not so limited and may comprise more than two conductive layers, depending on design requirements, e.g. five conductive metal layers. Also in the interest of illustrative convenience,
FIG. 1
does not illustrate any particular type of plug or barrier layer technology. However, such technology is conventional and, therefore, the details of such features are not set forth herein.
As device features continually shrink in size, various circuit parameters become increasingly important. For example, the capacitance between gate electrode
4
and source/drain regions
3
is an important parameter that affects circuit operating speeds. Generally, when the transistor is under operating conditions, the voltage on gate electrode
4
changes according to the circuit conditions. This results in charging and discharging source/drain regions
3
. Accordingly, any capacitance between gate electrode
4
and source/drain regions
3
slows the charging and discharging, and hence, slows the circuit operating speed.
In conventional semiconductor methodology illustrated in
FIG. 2
, after polysilicon gate electrode
4
is formed, ion implantation is conducted, as indicated by arrows
20
, to form shallow source/drain (S/D) extensions
22
. Subsequent to the formation of the S/D extensions
22
, a layer of dielectric material, such as silicon dioxide or silicon nitride is deposited and etched to form insulating sidewall spacers
24
on the side surfaces of gate electrode
4
, as shown in FIG.
3
. Adverting to
FIG. 3
, ion implantation is then conducted, as indicated by arrows
30
to form moderately-doped source/drain (MDD) or heavily-doped source/drain (HDD) implants
32
.
A drawback attendant upon the formation of conventional sidewall spacers
24
is that the material used to form the spacers typically has a relatively high dielectric constant (K), e.g., about 3.9 (oxide) to about 7.0 (nitride). These high-K materials increase the capacitance between gate electrode
4
and S/D extensions
22
, thereby slowing circuit operating speeds. It is not practical to employ materials having a low-K to form sidewall spacers, since typical low-K materials are not robust enough to shield shallow S/D extensions
22
from the subsequent impurity implantations forming MDD/HDD regions
32
. Further, typical low-K materials are not robust enough to prevent subsequent silicide formations from shorting the gate electrode to the source/drain areas. In high performance integrated circuits, such as those employed in microprocessors, capacitive loading must be reduced to as great an extent as possible to avoid reductions in circuit speed, without sacrificing circuit reliability.
SUMMARY OF THE INVENTION
There exists a need for a semiconductor device exhibiting reduced capacitance between the gate electrode and source/drain regions.
There is also a need for a method of manufacturing a semiconductor device having reduced capacitance between the gate electrode and source/drain regions.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the invention. The advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to one aspect of the invention, a semiconductor device comprises a semiconductor substrate and a dielectric layer formed on the semiconductor substrate. The semiconductor device includes a gate electrode having an upper surface and side surfaces formed on the dielectric layer. The semiconductor device also includes a first spacer, comprising a first material having a low dielectric constant, formed on the side surfaces of the gate electrode.
Another aspect of the present invention provides a method for manufacturing a semiconductor device. The method includes forming a first dielectric layer on a surface of a semiconductor substrate and forming a conductive layer on the dielectric layer. The method also includes patterning the conductive layer to form a gate electrode having an upper surface and side surfaces. The method further includes forming a first spacer, comprising a material having a low dielectric constant, on the side surfaces of the gate electrode.
Other features and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the invention. The invention is capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.


REFERENCES:
patent: 5200352 (1993-04-01), Pfiester
patent: 5319232 (1994-06-

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