Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-11-12
2004-04-06
Nguyen, Ha Tran (Department: 2812)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S624000, C438S637000, C438S725000, C438S780000
Reexamination Certificate
active
06716742
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to interconnect structures for high-speed microprocessors, application specific integrated circuits (ASICs), and other high-speed integrated circuits (ICs). The present invention provides low dielectric constant (i.e., low-k) interconnect structures having enhanced circuit speed, precise values of conductor resistance, and reduced fabrication cost. The structures of the present invention have a lower effective dielectric constant, improved control over metal line resistance, and reduced cost to fabricate compared to conventional structures of the prior art.
BACKGROUND OF THE INVENTION
Many low-k dielectrics having a dielectric constant of about 3.5 or less, plus Cu interconnect structures of the dual damascene-type are known; See, for example, R. D. Goldblatt, et al., “A High Performance 0.13 &mgr;m Copper BEOL Technology with Low-K Dielectric”, Proceedings of the International Interconnect Technology Conference, IEEE Electron Devices Society, Jun. 5-7, 2000, pgs 261-263. During fabrication of prior art interconnect structures, the depth of the trenches that become the metal conductors (after metal fill and chemical-mechanical polishing (CMP)) is often poorly controlled, and the trenches develop a shape known as a micro-trench. A pictorial representation of prior interconnect structures containing micro-trenches is shown in FIG.
1
. Specifically,
FIG. 1
comprises substrate
10
, low-k dielectric
12
, and metal filled conductor regions
14
which include diffusion barrier liner
16
. Note that the metal filled conductor region on the right-hand side of the figure includes micro-trench
18
.
A timed reactive-ion etch (RIE) process is used to etch the trenches, with time controlling the depth of the trench. Both the etch rate and shape of the trench profile typically vary with trench width (feature size) across the wafers, leading to large variations in trench depth which, in turn, leads to large variations in the metal conductor resistance. These variations in etch rate and feature shape may change over time (day to day).
The rough shape of the trench bottom also causes a reliability problem because the diffusion barrier liner has weak (thin) locations when it is deposited onto a rough surface in the trench. Common solutions to the above problem of micro-trenching include the use of additional processing steps, which raise the overall production cost of fabricating the desired low-k dielectric plus Cu interconnect structure.
Also, the fabrication of the interconnect structures with copper, Cu, and low-k materials currently entails the use of spin-on coating tools and more expensive plasma-enhanced chemical vapor deposition (PECVD) tools. The use of mixed sets of tooling increases equipment purchase and maintenance cost and the raw time for fabrication.
In view of the problems with the prior art, there is a need to provide a new and improved method of manufacturing a low-k dielectric plus metal interconnect structure which avoids the formation of micro-trenches.
SUMMARY OF THE INVENTION
One object of the present invention is to provide a low-k dielectric plus metal interconnect structure of the dual damascene-type in which precise and uniform control over the metal conductor resistance can be obtained.
Another object of the present invention is to provide precise control over the shape of the metal conductors to improve reliability without added processing cost.
A further object of the present invention is to provide an interconnect structure in which the metal conductor has a substantially flat bottom, i.e., no micro-trenches are present.
A yet further object of the present invention is to provide a low-k dielectric plus metal interconnect structure (with precise and uniform control over the metal conductor resistance) that is based on a multilayer of spin coated dielectric layers; therefore avoiding the use of costly vacuum-based deposition tools.
Another object of the present invention is to use porous dielectrics having a k of about 3.5 or less.
These and other objects and advantages are achieved in the present invention by providing an interconnect structure which includes at least a multilayer of dielectric materials which are applied sequentially in a single spin apply tool and then cured in a single step and a plurality of patterned metal conductors within the multilayer of spun-on dielectrics. The control over the conductor resistance is obtained using a buried etch stop layer having a second atomic composition located between the line and via dielectric layers of porous low-k dielectrics having a first atomic composition. The inventive interconnect structure also includes a hard mask which assists in forming the interconnect structure of the dual damascene-type. The first and second composition are selected to obtain etch selectivity of at least 10 to 1 or higher, and are selected from specific groups of porous low-k organic or inorganic materials with specific atomic compositions and other discoverable quantities.
Specifically, the inventive dual damascene structure comprises:
a substrate having a patterned multilayer of dielectrics formed thereon, said patterned multilayer of dielectrics including first and second porous low-k dielectrics which are separated from each other by a buried etch stop layer, said first and second porous low-k dielectrics having a first composition;
a polish stop layer formed on said patterned multilayer of dielectrics over said second porous low-k dielectric; and
a metal conductor formed within said patterned multilayer of dielectrics.
In one embodiment of the present invention, the first and second porous low-dielectrics are organic dielectrics, and the buried etch stop layer is an inorganic low-k dielectric material. In this embodiment of the present invention, the inorganic buried etch stop layer may be porous or non-porous, with preference given to porous inorganic buried etch stop layers.
In another embodiment of the present invention, the first and second porous low-k dielectrics are low-k inorganic dielectrics or inorganic/organic hybrid dielectrics such as methylsilsesquioxane (MSQ), and said buried etch stop layer is an organic low-k dielectric. In this embodiment of the present invention, the organic buried etch stop layer may be porous or non-porous, with preference given to non-porous materials.
The inventive structure offers the following advantages over prior art interconnect structures:
(i) Precise and uniform control of the metal conductor thickness and resistance.
(ii) Improved reliability because the trenches contain a diffusion barrier liner having a uniform thickness without weak points.
(iii) Highly controlled metal conductor resistance is obtained without added production cost, and with a reduction in the use of vacuum-based deposition tools.
Another aspect of the present invention relates to a method of fabricating the aforementioned low-k dielectric plus metal conductor interconnect structure which comprises the steps of:
(a) forming a multilayer of spun-on dielectrics on a surface of a substrate, said multilayer of spun-on dielectrics including first and second porous low-k dielectrics which are separated from each other by a buried etch stop layer, said first and second porous low-k dielectrics having a first composition, and said buried etch layer having a second composition which is different from said first composition;
(b) forming a hard mask on said multilayer of spun-on dielectrics, said hard mask including at least a polish stop layer and a patterning layer atop said polish stop layer;
(c) forming an opening in said hard mask so as to expose a surface of said multilayer of spun-on dielectrics;
(d) forming a trench level and a via level in said exposed surface of said multilayer of spun-on dielectrics using said hard mask as an etch mask;
(e) filling said trench level and via level with at least a conductive metal; and
(f) planarizing said conductive metal stopping on said polish stop layer formed on said multilayer of spun-on dielectrics.
In one embod
Gates Stephen McConnell
Hedrick Jeffrey Curtis
Nitta Satyanarayana V.
Purushothaman Sampath
Tyberg Cristy Sensenich
International Business Machines - Corporation
Morris Daniel P.
Nguyen Ha Tran
Scully Scott Murphy & Presser
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