Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-17
2003-02-25
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S421000, C438S422000, C438S634000, C438S778000, C257S642000, C257S758000, C257S759000, C257S760000
Reexamination Certificate
active
06524944
ABSTRACT:
TECHNICAL FIELD
The present invention generally relates to processing a semiconductor substrate by employing low k dielectric materials. In particular, the present invention relates to forming an advanced low k material by partially or entirely removing another dielectric material.
BACKGROUND ART
An integrated circuit consists of electronic devices electrically coupled by conductive trace elements called interconnect lines (interconnects). Interconnects are patterned from layers of electrically conductive materials (e.g., metals such as aluminum and/or copper, doped polysilicon, etc.) formed on the surface of a silicon wafer. Multiple layers (or levels) of closely-spaced interconnects allow an increase in the density of devices formed on semiconductor wafers. Electrical separation of stacked interconnect layers is achieved by placing an electrically insulating material (i.e., interlevel dielectric layer) between the vertically spaced interconnect layers. Multiple lines of closely-spaced interconnects on a single level also allow an increase in the density of devices formed on semiconductor wafers. Electrical separation of adjacent interconnect lines is achieved by placing an electrically insulating material (i.e., innerlayer dielectric) between the conductive interconnect lines.
Many types of materials are employed as insulating materials. Examples include oxides, silicates, nitrides, low k materials, and air. These insulating materials have different properties and characteristics; thus, different insulating materials are used depending upon the requirements of a given environment. Although air lacks the structural integrity of oxides, silicates, nitrides, and low k materials, air is the cheapest and has the lowest dielectric constant (about
1
). Therefore, in many instances it is desirable to employ air as an insulating material. The requirement of structural integrity, however, limits the extent to which air is employed in semiconductor manufacturing.
In very large scale integrated (VLSI) circuit devices, several wiring layers each containing numerous interconnect lines are often required to connect together the active and/or passive elements in a VLSI semiconductor chip. The interconnection structure typically consists of thin conductive lines separated by insulation in one layer or level and connected through vias or studs from contacts of the elements of the semiconductor chip or to a similar layer in another level of interconnections. With the trend to higher and higher levels of integration in semiconductor devices to ultra large scale integrated (ULSI) circuits, the space or gap between the wires or conductive lines to be filled with insulation is becoming extremely narrow, such as about 0.18 microns and smaller. In addition, when the height of the conductive lines is increased, it is more difficult to fill gaps between the lines, especially when the aspect ratio is 2 to 1 or greater with a gap distance of 0.25 microns or smaller.
In order to satisfy increasingly higher density requirements, the dimensions of integrated circuits are continuously reduced and, hence, the line widths of the conductors decreased into the submicron range. While the there is as trend for conductors to become narrower and narrower, there is also a trend for the spaces between conductors to become narrower and narrower. As a result, there is an increasing and unmet need for high performance insulation materials.
SUMMARY OF THE INVENTION
The present invention provides an advanced low k material by partially or entirely removing another dielectric material, thereby providing improved insulation in semiconductor devices. The advanced low k material of the present invention provides excellent insulation between metal lines (as an innerlayer dielectric) and between metal layers (as an interlevel dielectric).
One aspect of the present invention relates to a method of forming an advanced low k material between metal lines on a semiconductor substrate, involving the steps of providing the semiconductor substrate having a plurality of metal lines thereon; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; and at least one of heating or etching the semiconductor substrate whereby at least a portion of the spin-on material is removed, thereby forming the advanced low k material comprising at least one air void between the metal lines, the advanced low k material having a dielectric constant of about 2 or less.
Another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and at least one of heating or etching the semiconductor structure whereby at least a portion of the spin-on material is removed, thereby forming an advanced low k material comprising at least one air void, the advanced low k material having a dielectric constant of about 2 or less.
Yet another aspect of the present invention relates to a method of forming a semiconductor structure, involving the steps of forming a first plurality of metal lines on the semiconductor structure; depositing a spin-on material over the semiconductor substrate having the plurality of metal lines thereon, wherein the spin-on material is a silicate or a low k polymer material; forming a plurality of openings in the spin-on material exposing a portion of the metal lines and depositing metal to form a plurality of metal vias in the openings; forming a second plurality of metal lines over at least a portion of the metal vias; and heating the semiconductor structure whereby a portion of the spin-on material is removed, thereby forming a porous advanced low k material comprising a plurality of voids, the porous advanced low k material having a dielectric constant of about 1.75 or less.
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International Search Report.
Rangarajan Bharath
Subramanian Ramkumar
Templeton Michael K.
Amin & Turocy LLP
Chaudhuri Olik
Lee Hsien Ming
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