Low-K gate spacers by fluorine implantation

Details Low-K gate spacers by fluorine implantation Low-K gate spacers by fluorine implantation

2003-01-15

2004-04-13

Fahmy, Wael (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S230000, C438S303000

Reexamination Certificate

active

06720213

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates generally to the provision of low-K (reduced from 4.0 to approximately 3.3) gate sidewall spacers by fluorine implantation in a MOSFET device, and more particularly pertains to a MOSFET structure, and a method of fabrication thereof, having fluorine doped gate oxide sidewall spacers, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
Device feature scaling has associated fundamental problems which tend to degrade overall power dissipation including:
increased stud or via capacitance as a result of sidewall spacer thickness reduction;
increased overlap capacitance as a result of gate dielectric thickness scaling;
increased GIDL (gate-induced drain leakage) current as a result of a thinner gate dielectric in the gate-to-diffusion overlap region;
degraded dielectric breakdown at the gate edge.
SUMMARY OF THE INVENTION
The present invention provides a MOSFET device and a method of fabricating a MOSFET device having low-K dielectric gate oxide sidewall spacers formed by fluorine implantation. The present invention reduces the dielectric constant from approximately 4.0 to approximately 3.3, or to a value somewhere in the range between 3.3 and 4.0. The present invention implants fluorine into the gate oxide sidewall spacers which is used to alter the properties of advanced composite gate dielectrics e.g. nitridized oxides, NO, and gate sidewall dielectrics, such that the low-K properties of fluorine are used to develop low parasitic capacitance MOSFETs.
The low-K dielectric gate sidewall spacers result in reduced capacitance through the gate sidewall spacer. By appropriate selection of the fluorine implant dosage and energy, the dielectric constant of the gate dielectric in the gate-to-diffusion overlap region is also reduced, thereby reducing the overlap capacitance and the GIDL field in the Si at the drain diffusion. Furthermore, the reliability of the gate dielectric, particularly at the corner, is improved by the presence of the fluorine.
The present invention provides implantation of fluorine into the oxide spacers on the sidewalls of the gate conductors and provides a sacrificial protective layer over the substrate to block fluorine implantation into the substrate, and also provide an etch stop barrier to allow the removal of the sacrificial blocking layer without damaging the fluorinated spacers.


REFERENCES:
patent: 5571734 (1996-11-01), Tseng et al.
patent: 5677218 (1997-10-01), Tseng
patent: 5793088 (1998-08-01), Choi et al.
patent: 5872382 (1999-02-01), Schwalke et al.
patent: 6255703 (2001-07-01), Hause et al.
patent: 6285054 (2001-09-01), Liu et al.
patent: 6297106 (2001-10-01), Pan et al.
patent: 6358826 (2002-03-01), Hause et al.
patent: 6420220 (2002-07-01), Gardner et al.
patent: 6482726 (2002-11-01), Aminpur et al.
patent: 2000260989 (2000-09-01), None

Affiliated with

Also associated with

Rating

Low-K gate spacers by fluorine implantation does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low-K gate spacers by fluorine implantation, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low-K gate spacers by fluorine implantation will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3236635