Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2005-08-09
2005-08-09
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S634000, C438S740000
Reexamination Certificate
active
06927161
ABSTRACT:
A low-k dielectric layer stack is provided including a silicon based dielectric material with a low permittivity, wherein an intermediate silicon oxide based etch indicator layer is arranged at a depth that represents the depth of a trench to be formed in the dielectric layer stack. A thickness of the etch indicator layer is sufficiently small to not unduly compromise the overall permittivity of the dielectric layer stack. On the other hand, the etch indicator layer provides a prominent optical emission spectrum to reliably determine the time point when the etch process has reached the etch indicator layer. Thus, the depth of trenches in highly sophisticated low-k dielectric layer stacks may reliably be adjusted to minimize resistance variations of the metal lines.
REFERENCES:
patent: 6037664 (2000-03-01), Zhao et al.
patent: 6153511 (2000-11-01), Watatani
patent: 6238937 (2001-05-01), Toprac et al.
patent: 6511920 (2003-01-01), Nguyen et al.
patent: 6514856 (2003-02-01), Matsumoto
patent: 6548400 (2003-04-01), Brennan et al.
patent: 6593655 (2003-07-01), Loboda et al.
patent: 6624061 (2003-09-01), Aoki
patent: 19814703 (1999-01-01), None
patent: WO 00/19523 (2000-04-01), None
Wolf and Tauber; Silicon Processing for the VLSI Era vol. 1: Process Technology; pp. 73, 168, 183, 184, 198; Lattice Press 1986, Sunset Beach, CA.
Wolf, Stanley; Silicon Processing for the VLSI Era vol. 2: Process Integration; p. 194; Lattice Press 1990, Sunset Beach CA.
Miyamoto et al., “High-Speed and Low-Power Interconnect Technology for Sub-Quarter-Micron ASIC's,”IEEE Transactions on Electron Devices, 44:250-56, 1997.
Ruelke Hartmut
Streck Christof
Sulzer Georg
Advanced Micro Devices , Inc.
Fourson George
Toledo Fernando L.
Williams Morgan & Amerson P.C.
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