Low junction leakage mosfets with particular sidewall spacer str

Details Low junction leakage mosfets with particular sidewall spacer str Low junction leakage mosfets with particular sidewall spacer str

1997-08-11

1999-02-16

Fahmy, Wael

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257344, 257900, H01L 2976, H01L 2994, H01L 27088

Patent

active

058723820

ABSTRACT:
Shallow junction field effect transistors are made by a low temperature process comprising ion implanting source/drain regions through a buffer layer in two steps, the first an ion implant at high dosage and low energy and the second an ion implant at low dosage and high energy. Ion implantation through the buffer layer avoids crystallographic damage to the silicon substrate. By grading the sidewall spacers of the gate electrode, more or fewer ions can be implanted through the spacer foot to ensure continuity between the source/drain regions and the channel region under the gate electrode.

REFERENCES:
patent: 4558507 (1985-12-01), Okaybayashi et al.
patent: 4755479 (1988-07-01), Miura
patent: 5164801 (1992-11-01), Hieda et al.
patent: 5182619 (1993-01-01), Pfiester
patent: 5235204 (1993-08-01), Tsai
patent: 5278441 (1994-01-01), Kang et al.
patent: 5304827 (1994-04-01), Malhi et al.
patent: 5424571 (1995-06-01), Liou

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