Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Reexamination Certificate
2005-09-13
2011-12-27
Tran, Khanh C (Department: 2611)
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
C375S375000, C375S327000
Reexamination Certificate
active
08085893
ABSTRACT:
A clock recovery circuit includes a first phase detector for measuring the phase difference between a first clock signal from a voltage controlled oscillator (VCO) and a data signal. A phase shifter responsive to a control signal based on this phase difference adjusts the phase of an incoming clock signal to yield a second clock signal. The phase difference between the first clock signal and the second clock signal is measured and the resulting signal is low-pass filtered to derive a control signal for controlling the VCO. The phase locked loop including the VCO filters out jitter.
REFERENCES:
patent: 5937020 (1999-08-01), Hase et al.
patent: 5990714 (1999-11-01), Takahashi et al.
patent: 6617936 (2003-09-01), Dally et al.
patent: 6630868 (2003-10-01), Perrott et al.
patent: RE38482 (2004-03-01), Leung et al.
patent: 6861916 (2005-03-01), Dally et al.
patent: 6914465 (2005-07-01), Kiyose et al.
patent: 6950956 (2005-09-01), Zerbe et al.
patent: 2002/0037065 (2002-03-01), Nakamura
patent: 2002/0105386 (2002-08-01), Shastri
patent: 2003/0103591 (2003-06-01), Noguchi
patent: 2004/0052323 (2004-03-01), Zhang
patent: 2004/0223575 (2004-11-01), Meltzer et al.
patent: 2005/0231249 (2005-10-01), Tani
patent: 2008/0212730 (2008-09-01), Tang et al.
“Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design,” Behzad Razavi, ed., IEEE Press (1994), pp. 33-35.
Emami-Neyestanak, Azita, Samuel Palermo, Hae-Chang Lee and Mark Horowitz, “CMOS Transceiver with Baud Rate Clock Recovery, for Optical Interconnects,” Computer Systems Lab., Stanford, CA, Jun. 17-19, 2004.
Gursoy, Zafer Ozgur (ST Microelectronics), and Yusuf Leblebici (Swiss Federal Inst. of Tech.—Lausanne), “Design and Realization of a 2.4 Gbps—3.2 Gbps Clock and Data Recovery Circuit Using Deep-Submicron Digital CMOS Technology.” Jan. 2003.
Hogge, JR., Charles R., “A Self Correcting Clock Recovery Circuit,” J. of Lightwave Tech., vol. LT-3, No. 6, Dec. 1985.
Kim, Dong-Hee and Jin-Ku Kang, “A 1.0-Gbps Clock and Data Recovery Circuit with Two-XOR Phase-Frequency Detector,” Dept. of Electrical and Computer Engineering , Inha Univ., Inchon, Korea, Aug. 6, 2002.
Kim, Jaeha and Mark A. Horowitz, “Adaptive Supply Serial Links With Sub-1-V Operation and Per-Pin Clock Recovery,” IEEE J. of Solid-State Circuits, vol. 37, No. 11, Nov. 2002.
Larsson, Patrick, “A 2-600-MHz CMOS Clock Recovery PLL with Low-VddCapability,” IEEE J. of Solid-State Circuits, vol. 34, No. 12, Dec. 1999.
Lee, Haechang, Chi Ho Yue, Samuel Palermo, Kenneth W. Mai, and Mark Horowitz, “Burst Mode Package Receiver using a Second Order DLL,” Center for Integrated Systems, Stanford Univ., Stanford, CA, 2004.
Lee, Thomas H., “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop,” IEEE J. of Solid-State Circuits, vol. 27, No. 12, Dec. 1992.
Sidiropoulos, Stefanos and Mark Horowitz, “SA20.2: A Semi-Digital DLL with Unlimited Phase Shift Capability and 0.08-400MHz Operating Range,” Center for Integrated Systems, Stanford Univ., Stanford, CA, mos.stanford.edu.\papers\ss—1sscl—97.pdf, Feb. 1997.
Song, Yeo-San and Jin-Ku Kang, “A Delay Locked Loop Circuit With Mixed-Mode Tuning,” Dept. of Electrical and Computer Engineering, Inha Univ., Inchon, Korea, Sep. 2000.
Song, Yeo-San et al., A Delay Locked Loop Circuit with Mixed Mode Phase Tuning Technique, IEICE Trans. Fundaments, vol. E83-A, No. 9, Sep. 2000.
Toifl, Thomas, Christian Menolfi, Peter Buchmann, Marcel Kossel, Thomas Morf, Robert Reutemann, Michael Ruegg, Martin Schmatz, and Jonas Weiss, “0.94ps-rms-Jitter 0.016mm22.5GHz Multi-Phase Generator PLL with 360° Digitally Programmable Phase Shift for 10Gb/s Serial Links,” 2005 IEEE Int'l Solid-State Circuits Conference.
Wong, Koon-Lun Jackie, Hamid Hatamkhani, and Mozhgan Mansuri, “A 27-mW 3.6-Gb/s I/O Transceiver,” IEEE J. of Solid-State Circuits, vol. 39, No. 4, Apr. 2004.
Ghulamali Qutbuddin
Kreisman Lance M.
Mahamedi Paradice Kreisman LLP
Rambus Inc.
Tran Khanh C
LandOfFree
Low jitter clock recovery circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low jitter clock recovery circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low jitter clock recovery circuit will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-4296405