Low jitter clock for a physical media access sublayer on a...

Details Low jitter clock for a physical media access sublayer on a... Low jitter clock for a physical media access sublayer on a...

2005-06-28

2005-06-28

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S047000

Reexamination Certificate

active

06911842

ABSTRACT:
A programmable logic device (PLD) is provided that supports multi-gigabit transceivers (MGTs). The PLD includes one or more pairs of shared clock pads for receiving one or more high-quality differential clock signals. Dedicated clock traces couple each pair of shared clock pads to one or more MGTs on the PLD. Each MGT includes a clock multiplexer circuit, which allows one of the high-quality differential clock signals to be routed as a reference clock signal for the MGT. The clock multiplexer circuits are designed such that no significant jitter is added to the high-quality clock signals. The clock multiplexer circuits can also route general-purpose clock signals received by the PLD as lower quality reference clock signals for the MGTs. The reference clock signal routed by the clock multiplexer circuit can be stepped down to provide a reference clock for a physical coding sublayer of the MGT.

REFERENCES:
patent: 5260611 (1993-11-01), Cliff et al.
patent: 5446914 (1995-08-01), Paul et al.
patent: 6133750 (2000-10-01), Chan et al.
patent: 0 575 050 (1993-12-01), None
patent: 0 596 658 (1994-05-01), None

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