Low jitter and/or fast lock-in clock recovery circuit

Details Low jitter and/or fast lock-in clock recovery circuit Low jitter and/or fast lock-in clock recovery circuit

2005-11-15

2009-06-09

Odom, Curtis B (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S375000, C327S155000, C327S156000, C327S160000

Reexamination Certificate

active

07545900

ABSTRACT:
An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.

REFERENCES:
patent: 5841303 (1998-11-01), Takashi et al.
patent: 6351164 (2002-02-01), Yoshie
patent: 6498537 (2002-12-01), Watanabe
patent: 6735260 (2004-05-01), Eliezer et al.
patent: 2006/0008040 (2006-01-01), Vallet et al.
patent: 2007/0025490 (2007-02-01), Azadet et al.

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