Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1998-01-13
1999-04-27
Bowers, Charles
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438622, 438 2, 438625, 438695, 257 32, 257 39, 257 30, H01L 3922
Patent
active
058973672
ABSTRACT:
A high-temperature (10K) superconductive integrated circuit has a ground plane (2), an interlevel dielectric (6), and a low value resistor (18) to provide conductive paths to reduce parasitic circuit inductances, thereby increasing the speed and performance of the integrated circuit. The circuit also includes a high value resistor (20) connected between interconnect wires (34) to produce a desired resistance with a short distance between the interconnect wires (34), thereby significantly reducing the circuit area. A method of fabricating the integrated circuit includes depositing the interlevel dielectric (6) on the ground plane (2) in separate steps, depositing and etching the trilayer (12, 14, 16), etching the low value resistor (18) on the dielectric (6), depositing the high value resistor (20) at substantially the same level above the ground plane (2) as the interconnect wires (22) of the first wire layer (24), and etching the interconnect wires (34) of the second wire layer (32) on the high value resistor (20).
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Abelson Lynn A.
Elmadjian Raffi N.
Kerber George L.
Ladizinsky Eric G.
Bowers Charles
Nguyen Thanh
TRW Inc.
Yatsko Michael S.
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