Low impedance package for integrated circuit die

Details Low impedance package for integrated circuit die Low impedance package for integrated circuit die

1983-12-01

1987-07-14

James, Andrew J.

357 70, 357 68, H01L 2348, H01L 2330

Patent

active

046806130

ABSTRACT:
A low inductive impedance dual in-line package for an integrated circuit die incorporates a lead frame formed with a central opening without a die attach paddle. A ground plate forms the die attach plane spaced from and parallel with the lead frame. A dielectric layer is formed between the lead frame and ground plate. The lead frame is formed with a ground lead finger electrically coupled in parallel with the ground plate thereby providing a ground path through the ground plate with planar configuration to minimize inductive impedance to ground current and to minimize cross coupling between the electrically active lead fingers of the lead frame. In the preferred embodiment, the lead frame and ground plate are initially supported in a spaced parallel plane relationship by complementary spacing tab elements. During encapsulation, the encapsulation molding compound is introduced between the lead frame and ground plate to form the dielectric layer. A low impedance lead frame is also described in which the power lead finger and ground lead finger are at least 2.5 times wider than the signal lead finger for cooperating with the ground plane and for minimizing inductive reactance to power currents and ground currents. The package may be further stabilized by incorporating an internal decoupling capacitor. The invention is particularly applicable to dual in-line packages (DIP'S) and provides a method for extending DIP technology for high speed low inductance applications.

REFERENCES:
patent: 4023053 (1977-05-01), Shimizu et al.
patent: 4177480 (1979-12-01), Hintzmann et al.
patent: 4252864 (1981-02-01), Coldren
patent: 4454529 (1984-06-01), Philofsky et al.
patent: 4459607 (1984-07-01), Reid
patent: 4514750 (1985-04-01), Adams
patent: 4521828 (1985-06-01), Fanning
patent: 4551746 (1985-11-01), Gilbert et al.
Thermal Characteristics of 16 and 40 Pin Plastic DIL Packages by James A. Andrews, L. M. Mahalingam and Howard M. Berg, Motorola Semiconductor Group, 5005 E. McDowell Road, Phoenix, Ariz. 85008.
Automated Packaging of a Premolded Chip Carrier, by Dimity Grabbe, AMP Inc., Harrisburg, Pa. and Alan Keizer, The Jade Corporation, Huntingdon Valley, Pa.

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