Semiconductor device manufacturing: process – Chemical etching – Combined with the removal of material by nonchemical means
Patent
1996-02-28
1998-08-25
Chang, Ceila
Semiconductor device manufacturing: process
Chemical etching
Combined with the removal of material by nonchemical means
438692, 438694, H01L 21302
Patent
active
057983020
ABSTRACT:
The present invention is a semiconductor wafer that enhances polish-stop endpointing in chemical-mechanical planarization processes. The semiconductor wafer has a substrate with a device feature formed on the substrate, a stratum of low friction material positioned over the substrate, and an upper layer deposited on the low friction material stratum. The low friction stratum has a polish-stop surface positioned at a level substantially proximate to a desired endpoint of the chemical-mechanical planarization process. The upper layer, which is made from either a conductive material or an insulative material, has a higher polishing rate than that of the low friction stratum. In operation, the low friction stratum resists chemical-mechanical planarization with either hard or soft polishing pads to stop the planarization process at the desired endpoint.
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Hudson Guy F.
Zahorik Russell C.
Chang Ceila
Micro)n Technology, Inc.
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