Low energy memory component

Static information storage and retrieval – Read/write circuit – Data refresh

Reexamination Certificate

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Details

C365S185190, C365S226000

Reexamination Certificate

active

08054707

ABSTRACT:
The present invention is directed to a DRAM circuit that implements a self-refresh scheme to substantially reduce its power dissipation level during self-refresh operations. A ramped power supply voltage in replacement of a substantially invariant power supply voltage is used to power a sense amplifier in the DRAM circuit for amplifying a voltage difference between two bit lines coupled to the sense amplifier. As a result, the heat produced by the self-refresh operation is only a fraction of the heat produced by the conventional self-refresh powered by the substantially invariant power supply voltage.

REFERENCES:
patent: 2002/0097624 (2002-07-01), Andersen
patent: 2002/0118588 (2002-08-01), Kato
patent: 2002/0186598 (2002-12-01), Ooishi
patent: 2003/0189856 (2003-10-01), Cho et al.
patent: 0293933 (1988-12-01), None
International Search Report and Written Opinion issued in PCT/US2007/084217, Jul. 9, 2008, 9 pages.

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