Low energy differential logic gate circuitry having substantiall

Details Low energy differential logic gate circuitry having substantiall Low energy differential logic gate circuitry having substantiall

1994-06-03

1996-04-09

Westin, Edward P.

Electronic digital logic circuitry

Clocking or synchronizing of logic stages or gates

Field-effect transistor

327215, H03K 19094, H03K 3356

Patent

active

055065198

ABSTRACT:
An energy efficient logic gate circuit design that provides a substantially constant load to a clock source regardless of logic signal inputs to, or outputs from, the gate. The gate provides two complementary outputs and utilizes cross-coupled transistors to ensure that the outputs remain valid (complementary) after the logic inputs become invalid. Two blocks, each having a node coupling to the clock source and performing complementary logic functions, in combination with diodes for recharging the outputs of the gate, present the constant load to the clock source.

REFERENCES:
patent: 5144163 (1992-09-01), Matsuzawa et al.
patent: 5258666 (1993-11-01), Furuki
patent: 5382844 (1995-01-01), Knauer
patent: 5384493 (1995-01-01), Furuki

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