Low duty cycle distortion differential to CMOS translator

Details Low duty cycle distortion differential to CMOS translator Low duty cycle distortion differential to CMOS translator

2007-02-13

2007-02-13

Tan, Vibol (Department: 2819)

Electronic digital logic circuitry

Interface

Supply voltage level shifting

C326S081000, C330S261000

Reexamination Certificate

active

10798657

ABSTRACT:
Disclosed is a circuit comprising a differential input amplifier stage, a capacitor stage, an inverter chain stage, and a biasing circuit. The inverter chain stage may be formed with or without feedback depending on whether a clock signal or data signal is to be translated using the disclosed circuit. The biasing circuit can be formed using either inverters or transmission gates. Moreover, the biasing circuit, the inverter chain stage, and the amplifier stage can be connected to a power down circuit which, when the translator is not being used, will ensure various circuitry of the translator will not consume extensive power. The inverter chain stage, biasing circuit, and capacitor stage are formed on both an upper and lower section to produce true and complementary outputs that have a consistent and equal delay from the transitions of the incoming differential input signal so as to minimize jitter and associated duty cycle of the translated output.

REFERENCES:
patent: 4622480 (1986-11-01), Uchimura et al.
patent: 4893092 (1990-01-01), Okamoto
patent: 4906871 (1990-03-01), Iida
patent: 5677643 (1997-10-01), Tomita
patent: 5684429 (1997-11-01), Sanwo et al.
patent: 6518789 (2003-02-01), Gossmann

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