Low dropout linear regulator

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257373, 327564, H01L 2976, H01L 2994, H01L 31062, H01L 31119

Patent

active

056775580

ABSTRACT:
A low dropout linear regulator utilizing a vertical PNP transistor as its pass element, integrated with CMOS circuitry. The vertical PNP transistor includes a P-well formed in a lightly doped N type substrate for its collector. An N-type region formed in the P-well is its base and a P-type region formed in the N-type region is its emitter. The emitter receives a variable input supply and the collector provides a regulated output signal to the load being driven. As the input voltage diminishes to less than a diode drop above the output voltage, the vertical PNP transistor tries to saturate and its associated parasitic NPN transistor turns on. To limit the effects of the parasitic NPN transistor and maintain a regulated output, a current limiter is connected between the input and the collector of the NPN parasitic transistor. As the input voltage drops, the possibility of lateral current flow from the P-well of the vertical PNP transistor through the substrate to NMOS devices comprising the CMOS circuitry increases. A current diverter is connected to the body of each NMOS device to prevent the lateral currents from entering the sources and drains of the NMOS devices.

REFERENCES:
patent: 4812891 (1989-03-01), Bingham
patent: 4893157 (1990-01-01), Miyazawa et al.
patent: 5245202 (1993-09-01), Yasazaka
Sedra et al, Micro Electronic Circuits, p. 795, .COPYRGT.1982.
Muller et al, Device Electronics for IC's, p. 122, .COPYRGT.1986.
Sedra, Microelectronic Circuitsp. 798, 1986.

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