Low distortion logic level translator

Details Low distortion logic level translator Low distortion logic level translator

1999-08-27

2001-11-27

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Logic level shifting

C326S073000, C326S077000

Reexamination Certificate

active

06323683

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to logic level translators generally and, more particularly, to a low distortion logic level translator. BACKGROUND OF THE INVENTION
Electrical circuits function in many modes having different signal levels. Some of the modes used include RTL, ECL, TTL, and CMOS. A complex circuit or system may be designed so that signals of one mode must be interfaced to circuitry of a different mode. For instance, ECL on-off (
1
-
0
) states are represented by negative 0.95 volts and negative 1.71 volts, respectively. CMOS on-off (
1
-
0
) states are represented by positive 5 volts and 0 volts, respectively. A logic level translator circuit is used to interface circuitry of different modes.
FIG. 1
is a circuit diagram illustrating a conventional logic level translator
10
. The circuit
10
comprises a differential amplifier (i.e., Ql and Q
2
) and a BiCMOS inverter (i.e., M
2
, M
3
, M
4
, Q
4
). A differential input signal is applied at the input terminals
2
a
and
2
b
. The transistors Q
1
and Q
2
amplify the differential input signal and provide a single-ended intermediate signal at the collector of the transistor Q
2
. The buffer transistor Q
3
presents the intermediate signal to the BICMOS inverter. The single ended intermediate signal is inverted and presented at the output as a BiCMOS-level output signal.
FIG. 2
is a circuit diagram illustrating a conventional logic level translator
20
. The circuit
20
is used to convert an ECL signal into a CMOS signal. An ECL signal is presented to the base of the transistor Q
3
. The transistor Q
3
acts as a capacitor to couple the signal to the transistors Q
5
and Q
6
. The switching point for the circuit to change state is set by VREF at the base of the transistor Q
4
. The input signal alters the current flow in the transistor Q
5
. The current flow in the transistor M
3
is likewise changed. The transistors Ml, M
3
form a current mirror. Changes in the current flow in the transistor M
3
are mirrored in the transistor M
1
. When sufficient current flows through the transistor M
1
, the input of the CMOS buffer B
1
and the collector of the transistor Q
1
are pulled up. The transistor Q
7
prevents the transistor Q
1
from saturating. When current flow through the transistor M
1
drops, the transistor Q
1
pulls down the input of the CMOS inverter. The CMOS inverter B
1
converts the input levels to CMOS level signals.
The translator
10
immediately converts a differential input signal to a single-ended intermediate signal. Therefore, the translator
10
cannot be used when the differential relationship of the input is to be maintained in the output. The translator
20
likewise can only be used for single-ended signals. The translators
10
and
20
use a combination of bipolar and MOS devices. The bipolar devices must be matched to the MOS devices. Distortion can be large and is process sensitive. The use of bipolar devices hinders uses in purely digital applications.
SUMMARY OF THE INVENTION
The present invention concerns an apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a differential intermediate signal in response to a differential input signal. The second circuit may be configured to generate one or more output signals in response to the differential intermediate signal.
The objects, features and advantages of the present invention include providing an apparatus that may (i) be insensitive to process, voltage, and/or temperature, (ii) remain in saturation (i.e., high gain) even when fully switched, (iii) have a very simple output common mode control, (iv) operate with low supply voltages, (v) accept input signals which swing up to the positive supply rail without affecting performance, (vi) use only MOSFET devices, (vii) run at very high speeds with minimal increase in current consumption, and/or (viii) set the output common mode at the threshold of a CMOS inverter.


REFERENCES:
patent: 5027014 (1991-06-01), Bass et al.
patent: 5223753 (1993-06-01), Lee et al.
patent: 5485106 (1996-01-01), Drost et al.
patent: 5621340 (1997-04-01), Lee et al.
patent: 5682108 (1997-10-01), Min

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