Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified material other than unalloyed aluminum
Reexamination Certificate
2001-03-19
2002-07-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified material other than unalloyed aluminum
C438S618000, C438S637000, C438S638000
Reexamination Certificate
active
06424038
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic conductor structures, as employed within microelectronic fabrications. More particularly, the present invention relates to low dielectric constant microelectronic conductor structures with enhanced adhesion and attenuated electrical leakage, as employed within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly common in the art of microelectronic fabrication to employ when fabricating microelectronic fabrications microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials. For reference purposes, comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications are intended as dielectric materials typically having dielectric constants in a range of from about 2.0 to about 4.0. For comparison purposes, conventional dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications, such as but not limited to conventional silicon oxide dielectric materials, conventional silicon nitride materials and conventional silicon oxynitride materials as employed for forming microelectronic dielectric layers within microelectronic fabrication, typically have dielectric constants in a range of from about 4.0 to about 8.0.
Comparatively low dielectric constant dielectric materials as employed for forming microelectronic dielectric layers within microelectronic fabrications may include, but are not limited to, spin-on-polymer (SOP) dielectric materials, spin-on-glass (SOG) dielectric materials, amorphous carbon dielectric materials, fluorosilicate glass (FSG) dielectric materials and aerogel (i.e., air or insulating gas entrained) dielectric materials. As is understood by a person skilled in the art, comparatively low dielectric constant dielectric materials are desirable within the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications insofar as within such applications comparatively low dielectric constant dielectric materials provide microelectronic fabrications with enhanced microelectronic fabrication speed, reduced patterned microelectronic conductor layer parasitic capacitance and reduced patterned microelectronic conductor layer cross-talk.
While comparatively low dielectric constant dielectric materials are thus desirable in the art of microelectronic fabrication for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications, comparatively low dielectric constant dielectric constant dielectric materials are nonetheless not entirely without problems within microelectronic fabrications when employed for forming microelectronic dielectric layers interposed between the patterns of patterned microelectronic conductor layers within microelectronic fabrications. In that regard, and in particular with respect to damascene methods for forming within microelectronic fabrications microelectronic conductor structures comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, there is often observed within such microelectronic conductor structures decreased adhesion and enhanced electrical leakage.
It is thus desirable in the art of microelectronic fabrication to provide microelectronic conductor structures, and methods for fabrication thereof, comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with enhanced adhesion and attenuated electrical leakage.
It is towards the foregoing object that the present invention is directed.
Various methods have been disclosed in the art of microelectronic fabrication for forming microelectronic conductor structures, and in particular microelectronic conductor structures comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of comparatively low dielectric constant dielectric materials, with desirable properties in the art of microelectronic fabrication.
For example, Zhao et al., in U.S. Pat. No. 6,100,184, discloses a method for efficiently forming within a microelectronic fabrication a microelectronic conductor structure comprising a patterned microelectronic conductor stud layer contacting a patterned microelectronic conductor interconnect layer, wherein each of the patterned microelectronic conductor stud layer and the patterned microelectronic interconnect layer has formed adjacent thereto a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material. In order to realize the foregoing object, the method comprises a dual damascene method which employs: (1) a pair of patterned first microelectronic dielectric layers formed of a first comparatively low dielectric constant dielectric material which defines a via, having formed thereover; (2) a pair of patterned second microelectronic dielectric layers formed of a second low dielectric constant dielectric material which defines a trench contiguous with the via, and further wherein the patterned microelectronic conductor stud layer which contacts the patterned microelectronic conductor interconnect layer is formed within the via contiguous with the trench while employing a single chemical mechanical polish (CMP) planarizing method.
In addition, Zhao, in U.S. Pat. No. 6,071,809, discloses a related dual damascene method for forming within a microelectronic fabrication a microelectronic conductor structure comprising a patterned microelectronic conductor stud layer contiguous with a patterned microelectronic conductor interconnect layer, each having formed adjacent thereto a microelectronic dielectric layer formed of a comparatively low dielectric constant dielectric material, in part absent delamination within the microelectronic conductor structure. To realize the foregoing object, the dual damascene method employs when forming within the microelectronic conductor structure while employing a single chemical mechanical polish (CMP) planarizing method the patterned microelectronic conductor stud layer contiguous with the patterned microelectronic conductor interconnect layer a composite hard mask layer/polish stop layer comprising a silicon nitride polish stop material layer having formed thereupon a silicon oxide hard mask material layer.
Desirable in the art of microelectronic fabrication are additional methods through which there may be formed within microelectronic fabrications microelectronic conductor structures comprising patterned microelectronic conductor layers having formed interposed between their patterns microelectronic dielectric layers formed of low dielectric constant dielectric materials, with enhanced adhesion and attenuated electrical leakage.
It is towards the foregoing object that the present invention is directed.
SUMMARY OF THE INVENTION
A first object of the present invention is to provide a microelectronic conductor structure and a method for forming the microelectronic conductor structure.
A second object of the present invention is to provide a microelectronic conductor structure and a method for forming the microelectronic conductor structure in accord with the first object of
Bao Tien-I
Jang Syun-Ming
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