Low-density parity-check decoder apparatus

Details Low-density parity-check decoder apparatus Low-density parity-check decoder apparatus

2007-09-18

2010-11-02

Abraham, Esaw T (Department: 2112)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Digital data error correction

C714S786000, C714S799000

Reexamination Certificate

active

07827461

ABSTRACT:
A low-density parity-check (LDPC) decoder includes a plurality of bit node processing elements, and a plurality of check node processing elements. The LDPC decoder also includes a plurality of message passing memory blocks. A first routing matrix couples the plurality of bit node processing elements to the plurality of message passing memory blocks. A second routing matrix couples the plurality of check node processing elements to the plurality of message passing memory blocks. The first routing matrix and the second routing matrix enable each bit node to exchange LDPC decoding messages with an appropriate check node via a corresponding one of the message passing memory blocks.

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Shimizu et al., “Partially-Parallel LDPC Decoder Based on High-Efficiency Message-Passing Algorithm,” IEEE Conference on Computer Design (ICCD), Oct. 2005, San Jose, CA; available at www.iccd-conference.org/proceedings/2005/080—shimizu—partially.pdf.
Kim et al., “Parallel VLSI Architectures for a Class of LDPC Codes,” IEEE Int'l Symposium of Circuits and Systems (ISCAS), 2002; available at www-cdslab.ece.umn.edu/cdslab/library/papers/iscas—02a.pdf.

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