Low couple effect bit-line voltage generator

Details Low couple effect bit-line voltage generator Low couple effect bit-line voltage generator

2010-03-02

2011-12-13

Nguyen, Dang (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S149000, C365S104000

Reexamination Certificate

active

08077528

ABSTRACT:
A bit-line voltage generator is provided. The bit-line voltage generator includes a discharge enhanced bias source and a switch unit. The switch unit includes a clamp transistor having a source, a gate connected to the discharge enhanced bias source, and a drain receiving a voltage; a switch transistor having a gate receiving a control signal, a drain connected to the source of the clamp transistor, and a source connected to a memory array, wherein a parasitic capacitor exists between the gate and the source of the clamp transistor; a resistor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground; and a capacitor having a first terminal connected to the drain of the switch transistor, and a second terminal connected to ground, wherein a charge in the parasitic capacitor, when the switch transistor is turned on, is almost identical to that when the switch transistor is turned off, so that a couple effect between the switch unit and the discharge enhanced bias source is reduced, thereby stabilizing a bias applied to the memory array.

REFERENCES:
patent: 6529431 (2003-03-01), Kuo et al.
patent: 7710091 (2010-05-01), Huang
patent: 2004/0027172 (2004-02-01), Regev et al.
patent: 2008/0013394 (2008-01-01), Wu
patent: 2009/0261800 (2009-10-01), Pan

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