Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Patent
1997-03-06
1999-04-06
Robertson, David L.
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
G06F 1200
Patent
active
058931414
ABSTRACT:
The cache is turned on after every reset without the use of a software utility. For cold resets, the cache memory is kept off until the first software INT 19h is detected. During the INT 19h the cache is turned on. For a warm reset, the cache memory is turned on immediately after warm reset is detected.
REFERENCES:
patent: 4167782 (1979-09-01), Joyce et al.
patent: 4700330 (1987-10-01), Altman et al.
patent: 5157774 (1992-10-01), Culley
patent: 5210847 (1993-05-01), Thome et al.
patent: 5255374 (1993-10-01), Aldereguia et al.
patent: 5276852 (1994-01-01), Callander et al.
patent: 5325504 (1994-06-01), Tipley et al.
patent: 5367659 (1994-11-01), Iyengar et al.
patent: 5394529 (1995-02-01), Brown, III et al.
patent: 5414820 (1995-05-01), McFarland et al.
patent: 5423019 (1995-06-01), Lin
patent: 5428760 (1995-06-01), Ghori et al.
patent: 5440751 (1995-08-01), Santeler et al.
patent: 5551006 (1996-08-01), Kulkarni
Intel Corporation
Robertson David L.
LandOfFree
Low cost writethrough cache coherency apparatus and method for c does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low cost writethrough cache coherency apparatus and method for c, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low cost writethrough cache coherency apparatus and method for c will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1381897