Low cost symbol error correction coding and decoding

Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction

Reexamination Certificate

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Reexamination Certificate

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07487425

ABSTRACT:
Byte or symbol organized linear block codes are optimized in terms of reducing the number of ones in their parity check matrices by means of symbol column transformations carried out by multiplication by non-singular matrices. Each optimized symbol column preferably, and probably necessarily, includes a submatrix which is the identity matrix which contributes to low weight check matrices and also to simplified decoding procedures and apparatus. Since circuit cost and layout area are proportional to the number of Exclusive-OR gates which is determined by the number of ones in the check matrix, it is seen that the reduction procedures carried out in accordance with the present invention solve significant problems that are particularly applicable in the utilization of byte organized semiconductor memory systems. Reduced weight coding systems are also generated in accordance with weight reducing procedures used in conjunction with modified Reed Solomon codes. The decoding and encoding methods and apparatus are extendable to the inclusion of any number of check symbols.

REFERENCES:
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patent: 0300139 (1989-01-01), None
patent: 178717 (1985-09-01), None
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