Low cost silicon substrate with impurity gettering and latch...

Details Low cost silicon substrate with impurity gettering and latch... Low cost silicon substrate with impurity gettering and latch...

1999-03-30

2002-02-12

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Gettering of substrate

By implanting or irradiating

C438S524000, C257S617000

Reexamination Certificate

active

06346460

ABSTRACT:

TECHNICAL FIELD
The present invention relates to silicon substrates for CMOS processing, and more particularly to a low cost method of processing silicon wafers to provide substrates with impurity gettering and latch up protection.
BACKGROUND OF THE INVENTION
Silicon complimentary metal-oxide-semiconductor (CMOS) circuits are well known for their reliability and low power consumption. However, the process for manufacturing CMOS circuits is extremely complex, involving many chemical and mechanical process steps. Fortunately, the process is well suited to automation and mass production, allowing manufacturers to produce thousands of CMOS circuits for only a few dollars each. As a result, CMOS circuits are used in a wide variety of electronic devices including computers, watches, automobiles, telephones, cameras, etc.
Regardless of what electronic devices their circuits are used in, two persistent problems that many CMOS circuit manufacturers contend with are latch up and impurity contamination. As is well known in the art, latch up occurs when parasitic bipolar transistors, which are inherent in the structure of CMOS circuits, begin to conduct current in a positive feed-back loop, causing a short between the power supply and ground. When latch up occurs, the circuit malfunctions and may be permanently damaged.
The most common method of protecting against latch up is to manufacture the CMOS circuits on a silicon wafer that is highly doped with boron (referred to hereinafter as a p
+
substrate). A lightly doped epitaxial silicon layer (p
31
epi layer) is then grown on the front surface of the p
+
substrate. The CMOS circuits are fabricated in the p
−
epi layer while the p
+
substrate acts as “buried layer” beneath the circuits. This buried layer reduces the gain of the parasitic transistors. With reduced gains, the parasitic transistors are less likely to begin conducting current, and less likely drive each other in the event current does begin to flow.
However, p
+
silicon wafers are relatively expensive. In addition, the high concentration of boron in the p
+
substrate causes problems during later processing because the boron tends to diffuse out of the back surface of the wafer and deposit on the p
−
epi layer, thereby changing the electrical properties of the epi layer. This phenomenon is known as the “autodoping effect.” To combat the autodoping effect, manufacturers must employ an additional processing step to deposit silicon dioxide on the back surface of the wafer, which prevents the boron from diffusing out of the p
+
substrate. This additional processing step increases the cost of manufacturing.
Impurity contamination of the silicon wafer is a problem throughout the CMOS manufacturing process. However, despite the best efforts of manufacturers, a certain amount of contamination is virtually inevitable. Furthermore, as the size of CMOS circuits continues to shrink, the detrimental effect of even a small amount of contamination is magnified. Fortunately, at least some impurities that reach the silicon wafer can be neutralized through “gettering.” Gettering is a natural process by which defects in the crystal lattice attract impurities within the silicon. The impurities are attracted to the defects due to the strain the defects create in the crystal lattice. As a result, impurities tend to precipitate around the defects.
Manufacturers often take advantage of this gettering process by intentionally creating defects, or gettering sites, in the crystal lattice to attract contaminants away from the circuitry. A common way of creating these Bettering sites, known as “intrinsic gettering,” is to incorporate oxygen into the silicon during crystal growth. A subsequent heat treatment will cause the oxygen to diffuse away from the surface of the silicon wafers to form silicon dioxide clusters within the crystal structure. These clusters create strain fields in the crystal structure which serve to attract impurities. However, intrinsic gettering requires relatively precise control of the oxygen concentration during crystal growth to achieve the desired gettering effect. Furthermore, the additional heat treatment increases the cost of production.
Alternative gettering methods involve creating strain on the back of the silicon wafer to attract impurities away from the front of the wafer. For example silicon wafer manufacturers often sandblast the back surface of the wafer to damage the crystal lattice and thereby cause strain. Alternatively, a polysilicon layer is sometimes deposited on the back surface of the wafer to create strain within the crystal lattice. This method is known as “polysilicon back-seal.” However, each of these alternative methods involves additional process steps which increase the cost of production.
Moreover, one disadvantage shared by all of the above gettering methods is relatively low gettering efficiency. Because the gettering sites are formed relatively far away from the epi layer, impurities within or near the epi layer are less likely to be attracted to the sites than if the sites were disposed relatively close to the epi layer.
SUMMARY OF THE INVENTION
The invention provides a low cost method of manufacturing a silicon substrate having both impurity gettering and protection against CMOS latch up. The method includes performing a low energy implant of a selected acceptor ion to form a low resistivity buried layer closely adjacent the front surface of a silicon wafer. A low energy silicon implant is also performed to create a plurality of gettering sites closely adjacent the front surface. Subsequently, an epitaxial silicon layer is grown on the front surface. The buried layer provides protection against latch up for CMOS circuits fabricated in the epitaxial layer. In addition, the plurality of gettering sites attract impurities away from the circuitry.


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