Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-11-23
2001-07-10
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S315000, C365S182000, C365S051000
Reexamination Certificate
active
06259126
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a new memory structure for use in high density memory chips. In particular, the present invention provides a memory structure that includes non-volatile memory such as NVRAM memory structures and/or FERAM memory structures, and/or volatile memory such as DRAM and/or SRAM memory structures on one substrate. The present invention also includes a new NVRAM cell structure. Additionally, the present invention relates to processes for forming a memory structure that includes NVRAM, FERAM, DRAM, and/or SRAM memory structures on one substrate, and processes for forming a new NVRAM cell structure for system-on-chip (SOC) and/or embedded applications.
BACKGROUND OF THE INVENTION
Laser fusible redundancy technology plays a key role for improving the yield of today's high density memory chips. However, disadvantages exist associated with such technology. For example, devices produced according to the technology are bulky and costly in terms of chip area. The fuse blowing process that may occur in devices according to this technology may not operate as desired. The fuse blowing process is time consuming and unreliable, and the fuses are not reprogrammable.
As memory circuits become more sophisticated, it is often necessary to incorporate a block of EEPROM into other memory arrays, such as DRAM or SRAM. One example of such a device is a “smart card”. In a smart card, RAM serves as a scratch pad, ROM stores programs and runs the card's operating system, EEPROM includes user data, and a microcontroller allocates the memory and runs an encryption program. One example of a smart card is described in John Gallant, Smart Cards, EDN, Nov. 23, 1995, pp. 34-42, the entire disclosure of which is hereby incorporated by reference.
It is a great challenge to design a high density, small chip size, low cost smart card integrated circuit. Such devices have many inherent problems. For example, chip sizes larger than 0.25 mm
2
are prone to experiencing fractures when a card is flexed. Nevertheless, mixed memory process integration will become necessary in, for example, system-on-chip (SOC) applications, where CPU, SRAM type cache, programmable memory arrays, and/or random accessible memory arrays, and/or other devices are integrated in or on the same chip.
SUMMARY OF THE INVENTION
The present invention seeks to overcome the above problems as well as others by providing new memory structures and methods for making the structures.
The present inventors realized that it would be very desirable to replace the fuses described above with non-volatile memory. However, they also realized the difficulties in combining processes for forming different types of memory cells on the same substrate. Known processes for combining different types of memory cells involve many complex process steps, many extra masking levels and material layers to fabricate more than one type of memory cell on a single chip. The present inventors believe that such prior art processes are time consuming and costly, and that the resulting memory structures are non-planarized. Such non-planarized structures result in, for example, depth of focus, lithography, etch and deposition problems. An alternative approach integrated memory cells only on a system level, rather than on the same chip.
The present invention provides a solution to the above difficulties and problems by providing compatible memory cell structures and processes for forming different memory cell structure types on a single substrate.
The present invention also provides a new NVRAM cell structure.
According to preferred aspects, the present invention provides a semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure on a single substrate.
According to additional preferred aspects, the present invention provides a new NVRAM cell structure that includes an extended planarized floating gate.
According to further preferred aspects, the present invention provides a semiconductor memory device including at least three of the following cell structures: an NVRAM cell structure, an FERAM cell structure, a DRAM cell structure, and an SRAM cell structure on a single substrate.
According to other preferred aspects, the present invention provides processes for forming a semiconductor memory device including an NVRAM cell structure, a DRAM cell structure, and an SRAM cell structure on the same substrate and associated with a plurality of gate structures, including first polysilicon layers. The method includes depositing a second polysilicon layer over the gate structures. A floating gate of an NVRAM cell is formed by patterning the second layer of polysilicon over at least a stud interconnection connected to one of said gate structures on said substrate and associated with a first drain region and a first source region in the substrate. A capacitor of a DRAM cell or an SRAM cell is formed by patterning the second layer of polysilicon over at least a second drain region formed in the substrate. A thin layer of a dielectric is deposited over exposed surfaces of the patterned second polysilicon layer. A third layer of polysilicon is deposited on the patterned second polysilicon layer. A control gate of the NVRAM cell is formed by patterning the third polysilicon layer over the dielectric layer deposited on corresponding patterned portions of the second polysilicon layer. A ground plate of the DRAM cell or the body of a Thin-Film Transistor(TFT) SRAM cell is formed by patterning the third polysilicon layer over the dielectric layer deposited on corresponding patterned portions of the second polysilicon layer.
Preferred aspects of the present invention also include a process(es) to roughen the node dielectric of the DRAM together with the gate dielectric of the TFT device of the SRAM and floating gate dielectric of the NVRAM.
Another alternative aspect of this invention includes roughening only, for example, the node dielectric of the DRAM.
Furthermore, additional preferred aspects of the present invention include a semiconductor memory device formed according to various of the present inventive processes.
An additional alternative aspect of the present invention provides a semiconductor memory device including a Ferro-Electric RAM (FERAM) cell structure in lieu of or together with various of the other memory cell structures.
A further preferred aspect of the present invention includes a semiconductor memory device in which portions of the gates of at least two cell structures are substantially coplanar.
Still other objects and advantages of the present invention will become readily apparent to those skilled in the art from the following description and drawing figures. The detailed description and drawing figures show and describe preferred embodiments of the invention so as to illustrate the best mode contemplated for carrying out the invention. As those skilled in art will realize, the present invention includes other and different embodiments, for example, any combination(s) of the cell structures taught in this disclosure. Details of the invention may be modified in various respects, without departing from the invention.
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Assaderaghi Fariborz
Hsu Louis Lu-Chen
Mandelman Jack A.
Abate Esq. Joseph P.
Chaudhuri Olik
International Business Machines - Corporation
Pham Hoai
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