Low cost method of fabrication of vertical interconnections...

Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material

Reexamination Certificate

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C438S637000, C438S638000, C438S672000

Reexamination Certificate

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08062976

ABSTRACT:
A method is for forming a vertical interconnection through a dielectric layer between upper and lower electrically conductive layers of an integrated circuit. The method includes forming an opening through the dielectric layer and placing a solidifiable electrically conductive filler into the opening via a printing technique. The solidifiable electrically conductive filler is solidified to thereby form a solidified electrically conducting filler in the opening. A metallization layer is formed over the dielectric layer and the solidified electrically conducting filler to thereby form the vertical interconnection through the dielectric layer between the upper and lower electrically conductive layers of the integrated circuit.

REFERENCES:
patent: 5254872 (1993-10-01), Yoda et al.
patent: 7375774 (2008-05-01), Tanaka et al.
patent: 2005/0026421 (2005-02-01), Tanaka et al.
patent: 2005/0142871 (2005-06-01), Liu et al.
patent: 01/47044 (2001-06-01), None
patent: 02/29912 (2002-04-01), None
patent: 2006/061589 (2006-06-01), None

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