Low cost method of fabricating shallow junction, Schottky semico

Details Low cost method of fabricating shallow junction, Schottky semico Low cost method of fabricating shallow junction, Schottky semico

1995-03-28

1997-06-03

Niebling, John

Semiconductor device manufacturing: process

Gettering of substrate

438503, 438974, 438799, 117 97, H01L 21265

Patent

active

056354142

ABSTRACT:
Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

REFERENCES:
patent: 4376657 (1983-03-01), Nagasawa et al.
patent: 4711256 (1987-12-01), Kaiser
patent: 4878988 (1989-11-01), Hall et al.
patent: 5104828 (1992-04-01), Morimoto et al.
patent: 5110404 (1992-05-01), Fusegawa et al.
patent: 5130260 (1992-07-01), Suga et al.
patent: 5137597 (1992-08-01), Curry, II et al.
patent: 5190064 (1993-03-01), Aigo
patent: 5201958 (1993-04-01), Breunsbach et al.
patent: 5223080 (1993-06-01), Ohta et al.
patent: 5227339 (1993-07-01), Kishii
patent: 5240883 (1993-08-01), Abe et al.
patent: 5244819 (1993-09-01), Yue
patent: 5327007 (1994-07-01), Imura et al.
patent: 5360509 (1994-11-01), Zakaluk et al.
patent: 5389551 (1995-02-01), Kamakaura et al.
patent: 5419786 (1995-05-01), Kokawa et al.
"Flat Grinding of Semiconductor Wafers"--Hinzen; Semiconductors IDR 3, '92.
"A future technology for silicon wafer processing for ULSI"--Abe; Precision Engineering Oct. 1991, pp. 251-255.
"Backgrinding Wafers for Maximum Die Strength"--Lewis; Semiconductor International, Jul. 1992, pp. 86-89.
"Internal gettering heat treatments and oxygen precipitation in epitaxial silicon wafers"--Wijaranakula, Burke and Forbes; Journal of Materials Research, vol. 1, No. 5, Sep./Oct. 1986, pp. 693-697.
"Epi's Leading Edge"--Burggraaf; Semiconductor International, Jun. 1991, pp. 68-71.
"Mirror Surface Grinding of Silicon Wafer with Electrolytic in Process Dressing"--Ohmori and Nakatawa--date unknown.
"Wafer Gettering: The Key to Higher Yields?"--Peter H. Singer, Assoc. Editor, Semiconductor International; Feb. 1983 pp. 67-71.
S.K. Ghandi--"SemiconductorPower Devices", John Wiley & Sons, N.Y., 1977, pp. 290-239 (Chapter 6.3.1).
"Intrinsic Gettering in Heavily Doped Si Substrates for Epitaxial Devices"--Pearce and Rozgony; pp. 53-59.
"Latch-Up and Image Crosstalk Suppression by Internal Gettering"--Anagnostopoulos et al.; IEEE Transactions on Electron Devices, vol. ED-31, No. 2, Feb. 1984, pp. 225-231.
"Defect Engineering as an Important Factor in Developing VLSI Substrates"--Richter et al., 1982; Physics 116B (1983) pp. 162-167 North-Holland Publishing Co.
"Denuded Zone Stability in a SPAD Diode as a Function of Out-Diffusion Parameters"--Poggi et al.; IEEE Transactions of Electronic Devices, vol. ED-34, No. 7, Jul. 1987, pp. 1496-1500.
"Influence of Epi-Substrate Point Defect Properties on Getter Enhanced Silicon Epitaxial Processing for Advance CMOS and Bipolar Technologies"--Borland et al.; pp. 93-106.
"Extrinsic Gettering via Epitaxial Misfit Dislocations: Electrical Characterization"--Salih et al.; Journal of Electrochem. Soc.: Electrochemical Science and Technology, vol. 133, No. 3, Mar. 1986, pp. 475-478.
"Denuded Zones in Czochralski Silicon Wafers"--Wang et al.; J. Electrochem. Soc.: Solid-State Science and Technology, vol. 131, No. 8, Aug. 1984, pp. 1948-1952.
"Electrically Active Stacking Faults in Silicon"--Ravi et al.; J. Electrochem. Soc.: Solid State Science and Technology, vol. 120, No. 4, Apr. 1973, pp. 533-541.
"Oxidation-Induced Point Defects in Silicon"--Antoniedis; J. Electrochem. Soc.: Solid State Science and Technology, vol. 129, No. 5, May 1982, pp. 1093-1097.
"Internal Gettering in Czochralski Silicon"--Craven; Semiconductor International, Sep. 1985, pp. 134-139.
"Advanced CMOS Epitaxial Processing for Latch-Up Hardening and Improved Epilayer Quality"--Borland and Deacon; Solid State Technology, Aug. 1984, pp. 123-131.

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