Low cost DRAM metallization

Details Low cost DRAM metallization Low cost DRAM metallization

1998-03-11

2000-10-24

Clark, Sheila V.

Active solid-state devices (e.g., transistors, solid-state diode

Combined with electrical contact or lead

Of specified material other than unalloyed aluminum

257768, 257751, H01L 2348, H01L 2352, H01L 2940

Patent

active

061371807

ABSTRACT:
Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.

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