Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Patent
1995-12-28
1998-12-08
Everhart, Garidad
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
438649, 438675, 438680, H01L 21441
Patent
active
058468811
ABSTRACT:
Disclosed is a low cost contact and interconnect layer and method for fabricating the same. A contact via is opened within an insulating layer, exposing a circuit node (e.g., transistor active area within a semiconductor substrate). The via is filled with a chemical vapor deposited (CVD) titanium silicide layer, forming electrical contact with the circuit node. The silicide layer may simultaneously form the interconnect layer for one embodiment. In other embodiments, the interconnect layer may comprise a metal strap over the titanium silicide layer, or a metal layer over an etched-back titanium silicide plug in the contact via. For any of these embodiments, the contact via may be opened after the formation of interconnect trenches, the via extending from the bottom of a trench to the circuit node. CVD provides good step coverage of the via within the trench, despite the higher aspect ratio. The interconnect layer is deposited and etched back, such that the interconnect lines are defined by the trenches.
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Sandhu Gurtej S.
Sharan Sujit
Everhart Garidad
Micro)n Technology, Inc.
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