Low-cost cache coherency for accelerators

Details Low-cost cache coherency for accelerators Low-cost cache coherency for accelerators

2006-03-23

2010-10-12

Verbrugge, Kevin (Department: 2189)

Electrical computers and digital processing systems: memory

Storage accessing and control

Hierarchical memories

C711SE12026

Reexamination Certificate

active

07814279

ABSTRACT:
Embodiments of the invention provide methods and systems for reducing the consumption of inter-node bandwidth by communications maintaining coherence between accelerators and CPUs. The CPUs and the accelerators may be clustered on separate nodes in a multiprocessing environment. Each node that contains a shared memory device may maintain a directory to track blocks of shared memory that may have been cached at other nodes. Therefore, commands and addresses may be transmitted to processors and accelerators at other nodes only if a memory location has been cached outside of a node. Additionally, because accelerators generally do not access the same data as CPUs, only initial read, write, and synchronization operations may be transmitted to other nodes. Intermediate accesses to data may be performed non-coherently. As a result, the inter-chip bandwidth consumed for maintaining coherence may be reduced.

REFERENCES:
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patent: 2004/0230750 (2004-11-01), Blake et al.
patent: 2006/0179277 (2006-08-01), Flachs et al.
O. Takahashi et al., The Circuit Design of the Synergistic Processor Element of a Cell Processor, Nov. 2005, IEEE, p. 111.

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