Low cost built-in self test state machine for general...

Details Low cost built-in self test state machine for general... Low cost built-in self test state machine for general...

2005-09-06

2005-09-06

Decady, Albert (Department: 2133)

Error detection/correction and fault detection/recovery

Pulse or data error handling

Memory testing

C714S030000, C365S201000, C326S046000

Reexamination Certificate

active

06941495

ABSTRACT:
A system and method for creating a built-in self-testing (BIST) state machine to test random access memories (RAMs) are disclosed. The BIST state machine can be simplified to a simple four-state state machine while accommodating a large group of test suites by programming each state to have the capability of performing one of four necessary operations. These operations include a write operation, a read operation, a read/write operation and a null operation. Further bits and signals can be added to the state machine to enable an even larger array of test suites to be performed.

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V.D. Agrawal et al., “An Architecture for Synthesis of Testable Finite State Machines”, Mar. 12-15, 1990, EDAC Conference 1990, pp 612-616.

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