Electrical computers and digital processing systems: memory – Storage accessing and control – Control technique
Reexamination Certificate
2007-10-23
2007-10-23
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Control technique
C714S006130
Reexamination Certificate
active
10859826
ABSTRACT:
An architecture, method and apparatus for a data processing system having memory compression and two common memories forming either a single unified memory, or a dual memory system capable of continuous operation in the presence of a hardware failure or redundant “duplex” computer maintenance outage, without the cost of duplicating the memory devices. A memory controller employs hardware memory compression to reduce the memory requirement by half, which compensates for the doubling of the memory needed for the redundant storage. The memory controller employs error detection and correction code that is used to detect storage subsystem failure during read accesses. Upon detection of a fault, the hardware automatically reissues the read access to a separate memory bank that is logically identical to the faulty bank. After a memory bank is identified as faulty, the memory controller precludes further read access to the bank, permitting replacement without interruption to the application or operating system software operation.
REFERENCES:
patent: 5784548 (1998-07-01), Liong et al.
patent: 5928367 (1999-07-01), Nelson et al.
patent: 6442659 (2002-08-01), Blumenau
Bland Patrick Maurice
Smith, III Thomas Basil
Tremaine Robert Brett
Wazlowski Michael Edward
Jennings, Esq. Derek S.
Nguyen Hiep T.
Scully , Scott, Murphy & Presser, P.C.
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