Low cost alternative to large dual port RAM

Details Low cost alternative to large dual port RAM Low cost alternative to large dual port RAM

2000-11-15

2001-11-06

Nelms, David (Department: 2818)

Static information storage and retrieval

Addressing

Multiple port access

C365S189011, C365S189020, C365S221000, C365S230020

Reexamination Certificate

active

06314047

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is digital data storage and particularly dual port memories.
BACKGROUND OF THE INVENTION
The present invention deals with the data storage in digital signal processor chips having multiple processor-memory nodes. Conventional techniques would use a dual-port SRAM for a read and a write to be accomplished on a single clock cycle. Using a single port SRAM is normally much too restrictive and limits throughput by allowing only a read or a write in a given clock cycle. The bit cell size for a dual-port SRAM, however, is considerably larger typically four times as large as a cell for a single port SRAM. When a large SRAM is required, this is a significant silicon overhead.
One conventional technique which has been used to circumvent this limitation is to use a single port SRAM running at twice the frequency of the surrounding logic. This allows a simple time division multiplexing system to be used around the SRAM so that to the surrounding logic the SRAM appears dual ported. Each of the two-processor entities needing access to the SRAM appears to get it each cycle. In fact, one processor gets access in the first half of the cycle of the main clock and the second processor in the latter half. This works well at moderate clock speeds. However, if processor clock speed is itself aggressively high getting the SRAM to run at twice that speed is often not possible.
SUMMARY OF THE INVENTION
This invention makes possible -the implementation of certain dual port memory node functions using a considerably simplified and efficient approach employing single port SRAM and a wrapper interface. These parts together use less silicon area than conventional dual port SRAM techniques. This allows for more straightforward read-write operations during a single clock cycle, which make up the data storage and data retrieval process. The inventive technique, operating at the main processor clock frequency, achieves performance comparable to dual port SRAM operating at double the main processor clock frequency.
The invention is particularly applicable in system designs with a SRAM organized in multiple banks, all of which might be accessed at once. In the preferred embodiment the main central processing unit accesses two of the banks every cycle, and a centralized data transfer controller needs access to one bank. If both entities require access to different banks, the operation proceeds smoothly, but if both entities required access to the same bank there would be a conflict. The clear preference is to avoid having to stall either processor entity.
The present invention employs a wrapper around the multiple banks of SRAM which is accessed by both a central processing unit and a data transfer bus node of a data transfer controller simultaneously. This wrapper buffers data and serializes it for access to the SRAM banks. There is at least one bank of SRAM that is not being accessed directly on each cycle, and this cycle can be used for any buffered access encountered in earlier cycles.
While the system does not completely eliminate the need to stall the central processing unit due to a bank access conflict and the buffer holding queued accesses that conflicted in previous cycles may fill up, the system does significantly reduce the need for stalls.
The preferred embodiment employs four banks of SRAM but it can be generalized to down to a two-bank system where each of the devices needs access to one bank in each cycle. The probability that the two devices both want access to the same bank on many consecutive cycles is very low. This is especially true with a data transfer controller which tends to transfer data sequentially and tends to alternate between the banks.
For small SRAMs, the device area required to implement this technique would probably be more than that of just using a dual port SRAM. However, for large SRAMs this invention will prove cost effective.


REFERENCES:
patent: 5999478 (1999-12-01), Proebsting
patent: 403157890A (1991-07-01), None

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