Error detection/correction and fault detection/recovery – Pulse or data error handling – Data formatting to improve error detection correction...
Reexamination Certificate
2008-07-01
2008-07-01
Chaudry, Mujtaba K. (Department: 2112)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Data formatting to improve error detection correction...
C714S702000, C714S755000
Reexamination Certificate
active
07395461
ABSTRACT:
An interleaver has an input multiplexer that receives a data sequence at an interleaver input and that separates the data sequence into multiple data sub-blocks. The interleaver has a linear feedback shift register that generates an input address sequence. The interleaver has adder circuits that generate output address sequences associated with each data sub-block. The interleaver has memory that stores the data sub-blocks at addresses controlled by the input address sequence. The memory reproduces each data sub-block in an interleaved sequence controlled by the associated output address sequence. The interleaver has an output multiplexer that assembles the interleaved sequences to provide an interleaver output.
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Argon Cenk
Born Richard Martin
Silvus Gregory Lee
Souvignier Thomas Victor
Vasiliev Peter Igorevich
Chaudry Mujtaba K.
Seagate Technology LLC
Westman Champlin & Kelly P.A.
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