Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2006-02-21
2006-02-21
Zarabian, Amir (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S110000, C257S120000, C257S128000, C257S173000, C257S174000, C257S355000, C257S360000, C257S362000, C257S363000, C257S546000, C257S548000, C257S550000, C257S917000
Reexamination Certificate
active
07002218
ABSTRACT:
An ESD-protection structure is located substantially under an integrated circuit bond pad. This ESD-protection structure is formed as a low capacitance structure by inserting a forward diode between the bond pad and the ESD clamp circuit. Placing the ESD-protection structure under the bond pad eliminates parasitic substrate capacitance and utilizes a parasitic PNP transistor formed from the inserted forward biased diode. The ESD-protection structure includes adjacent alternating P+ and N+ diffusions located substantially under a bond pad to be ESD protected. The P+ diffusions are connected to the bond pad metal with metal vias through an insulating layer. The N+ diffusions are adjacent to the P+ diffusions. An N+ diffusion surrounds the N+ and P+ diffusions, and ties together the N+ diffusions so as to form a continuous N+ diffusion completely around each of the P+ diffusions. An N− well is located substantially under the N+ and P+ diffusions. The surrounding N+ diffusion partially overlaps the edge of the N− well below it. An outer portion of the N+ diffusion, the portion overlapping the N− well, is within a P− well. Another N+ diffusion encircles the N+ diffusion surrounding the P+ diffusions. The another N+ diffusion is in the P− well and a field oxide may be located between the N+ diffusion and the another N+ diffusion. An NPN field transistor is formed with the N+ diffusion being the transistor collector, the P− well being the transistor base and the another N+ diffusion being the emitter.
REFERENCES:
patent: 4642667 (1987-02-01), Magee
patent: 5166089 (1992-11-01), Chen et al.
patent: 5181091 (1993-01-01), Harrington et al.
patent: 5684322 (1997-11-01), Bernier
patent: 5719733 (1998-02-01), Wei et al.
patent: 5932914 (1999-08-01), Horiguchi
patent: 6060752 (2000-05-01), Williams
patent: 6215157 (2001-04-01), Fukuda
patent: 6271999 (2001-08-01), Lee et al.
patent: 6281428 (2001-08-01), Chiu et al.
patent: 6441439 (2002-08-01), Huang et al.
patent: 6576934 (2003-06-01), Cheng et al.
patent: 6833592 (2004-12-01), Lee
patent: 2004/0075144 (2004-04-01), Zitouni et al.
patent: 2004/0217425 (2004-11-01), Brodsky et al.
patent: 2004/0251502 (2004-12-01), Reddy et al.
patent: 2005/0045909 (2005-03-01), Zhang
Baker & Botts L.L.P.
Microchip Technology Incorporated
Soward Ida M.
Zarabian Amir
LandOfFree
Low capacitance ESD-protection structure under a bond pad does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Low capacitance ESD-protection structure under a bond pad, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low capacitance ESD-protection structure under a bond pad will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3628514