Low-capacitance contact for long gate-length devices with...

Details Low-capacitance contact for long gate-length devices with... Low-capacitance contact for long gate-length devices with...

2009-05-19

2010-10-12

Quach, Tuan N. (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

C438S197000, C438S618000, C257SE21409

Reexamination Certificate

active

07811871

ABSTRACT:
Disclosed are planar and non-planar field effect transistor (FET) structures and methods of forming the structures. The structures comprise segmented active devices (e.g., multiple semiconductor fins for a non-planar transistor or multiple semiconductor layer sections for a planar transistor) connected at opposite ends to source/drain bridges. A gate electrode is patterned on the segmented active devices between the source/drain bridges such that it has a reduced length between the segments (i.e., between the semiconductor fins or sections). Source/drain contacts land on the source/drain bridges such that they are opposite only those portions of the gate electrode with the reduced gate length. These FET structures can be configured to simultaneously maximize the density of the transistor, minimize leakage power and maintain the parasitic capacitance between the source/drain contacts and the gate conductor below a preset level, depending upon the performance and density requirements.

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