Active solid-state devices (e.g. – transistors – solid-state diode – Incoherent light emitter structure – With housing or contact structure
Reexamination Certificate
1999-07-12
2002-10-15
Cuneo, Kamand (Department: 2827)
Active solid-state devices (e.g., transistors, solid-state diode
Incoherent light emitter structure
With housing or contact structure
C257S773000
Reexamination Certificate
active
06465811
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This patent relates to fabrication of low-capacitance bonding pads for high-speed optical semiconductor devices such as lasers, detectors, and modulators.
2. Description of the Related Art
For many high-speed optical semiconductor devices, such as lasers, detectors and modulators, pad capacitance is often the greatest inhibitor to achieving higher data rates of operation. The pad capacitance has previously been removed, or largely eliminated, from high-speed devices using a number of techniques.
One such technique uses an air-bridge to connect a deposited top-level contact metal to a pad level metal when the pad metal is on a semi-insulating layer. One way of making suitable air-bridges is described in U.S. Pat. No. 5,219,713 issued Jun. 15, 1993 entitled “Multi-Layer Photoresist Air Bridge Fabrication Method”.
According to another technique, contact metal is deposited on a thick polyamide insulating layer. Because the polyamide is non-planar, special metal deposition techniques and often electroplating are required to build up the necessary thickness of the metal.
Although both techniques are useful, they are somewhat complicated, difficult to achieve in high yield, and may provide poor adhesion for subsequent wire or flip-chip bonding.
SUMMARY OF THE INVENTION
The invention relates to a technique for achieving low-capacitance bonding pads for high-speed optical semiconductor devices such as lasers, detectors and modulators. The invention is particularly useful in creating low-capacitance bonding pads for vertical cavity surface emitting lasers (VCSELs).
A typical VCSEL structure generally includes an active medium and a current confining region sandwiched between an upper and a lower mirror stack. An upper metal contact is located at the top of the upper mirror stack and normally includes an aperture for the emission of light from the laser. A lower metal contact is typically located below the level of the active medium so that current flow from the upper contact passes through the current confining region and the active medium to the lower metal contact.
In the structure according to the invention, the metal contact area, the associated metal bonding pad and the interconnecting metal bridge are deposited on top of the upper mirror stack which is also conductive. To prevent current flow from the pad through the conductive mirror stack which would bypass the active medium, a moat is etched surrounding the pad area. This moat isolates the pad metal portion and the conductive material beneath the pad metal portion. Since it is electrically isolated by the moat, the layered material beneath the pad metal portion can be electrically conductive, insulating or semiconducting. The moat also undercuts the interconnecting metal bridge which connects the pad area to the contact area.
For the purposes of this application, the term, “semiconductor layers” is defined as including the layered material between or adjacent the metal contact surfaces. In a typical VCSEL, the semiconductor layers would include the active medium, the current confining region and the mirror stacks. In other types of lasers, detectors and modulators, the semiconductor layers between or adjacent the metal contacts could include various combinations of semiconducting, conducting or insulating layers.
In the method according to the invention, the semiconductor layered portion of the optical semiconductor device is first formed on a suitable substrate. These semiconductor layers can include various layers of electrically conductive, semiconductive or insulating material as may be required for the type of device being constructed. The metal contact and the metal bonding pad areas together with an interconnecting metal bridge are then deposited on the surface of the semiconductor layers. The structure is then etched down from the top surface to form a moat surrounding the bonding pad area which electrically isolates the semiconductor layered material beneath the bonding pad and to undercut the material beneath the interconnecting bridge.
An alternative method is to form the semiconductor layers and then etch the areas surrounding the bonding pad from the bottom upwardly toward the metal bonding pad. According to this method the etch need only go high enough to prevent the current flow bypassing the active medium of the optical semiconductor device. In other words, the moat need only go as deep as required to cut off the bypassing current flow. Once the moat has been formed, the structure is completed by securing it to a suitable substrate.
REFERENCES:
patent: 4309670 (1982-01-01), Burnham et al.
patent: 5115442 (1992-05-01), Lee et al.
patent: 5219713 (1993-06-01), Robinson
patent: 5243200 (1993-09-01), Kawasaki et al.
patent: 5295147 (1994-03-01), Jewell et al.
patent: 5308440 (1994-05-01), Chino et al.
patent: 5327448 (1994-07-01), Holonyak, Jr. et al.
patent: 5331654 (1994-07-01), Jewell et al.
patent: 5403775 (1995-04-01), Holonyak, Jr. et al.
patent: 5404025 (1995-04-01), Yamada
patent: 5536971 (1996-07-01), Oishi et al.
patent: 5567982 (1996-10-01), Bartelink
patent: 5686743 (1997-11-01), Lammert
patent: 5699375 (1997-12-01), Paoli
patent: 5754578 (1998-05-01), Jayaraman
patent: 5789817 (1998-08-01), Richards et al.
patent: 5897329 (1999-04-01), Jewell
patent: 5903589 (1999-05-01), Jewell
patent: 5915168 (1999-06-01), Salatino et al.
patent: 0 809288 (1997-11-01), None
patent: 2211986 (1989-07-01), None
Geske Jonathan
Peters Frank
Cruz Lourdes
Cuneo Kamand
Genco Victor M.
Gore Enterprise Holdings Inc.
Sheets Eric J.
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