Low bitline capacitance structure and method of making same

Details Low bitline capacitance structure and method of making same Low bitline capacitance structure and method of making same

2001-01-17

2002-07-30

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having schottky gate

C438S740000, C438S761000

Reexamination Certificate

active

06426247

ABSTRACT:

FIELD OF INVENTION
The present invention relates to a method to fabricate high density dynamic random access memories (DRAMs). In specific, it relates to a method to fabricate such DRAMs having reduced bitline capacitance.
BACKGROUND OF THE INVENTION
Both static random access memory (SRAM) and dynamic random access memory (DRAM) have one or more arrays of memory cells organized into rows (wordlines) and columns (bitlines). Each memory cell represents a single bit and is accessed by a unique address defined by the intersection of a row and a column. Reading data from or writing data to memory cells is achieved by activating selected wordlines and bitlines. In DRAMs, each input/output pin is connected to each memory cell via a “sense amplifier”, which usually is one or more transistors configured to hold and amplify the charge to be read from or written to the cell. The sensitivity of the sense amplifier is proportional to the ratio of the capacitance of the node to the capacitance of the sensing bitline. Hence, it always is beneficial to have higher node capacitance or lower bitline capacitance (the bitline capacitance includes components of bitline to adjacent bitline, junction capacitance, and bitline to wordline capacitance).
As DRAMs are manufactured with increasing densities, the memory cells necessarily are made smaller and smaller and packed closer and closer together to pack as much memory into as small a space as possible. The increased density drives the bitlines closer together increasing the coupling between adjacent bitlines and also the coupling between bitlines and wordlines. This increased bitline capacitance makes it more difficult to detect the logical “0” or logical “1” in the memory cell.
SUMMARY OF THE INVENTION
Now, according to the present invention, a high density dynamic random access memory having substantially reduced bitline capacitance is provided, and, a method of fabricating such a DRAM device. This novel device is achieved mainly by reducing bitline contact to an active wordline capacitance. The proposed process offers advantages of (a) reduced aspect ratio of bitline etches, (b) reduced bitline to bitline leakage to thereby allow gap fills of lower reflow temperature, (c) reduced array junction leakage by utilizing a self-aligned polysilicon diffused junction for planar array transistors, and (d) improved support device rolloff characteristics due to use of raised source-drain junctions.


REFERENCES:
patent: 5518961 (1996-05-01), Ishimaru
patent: 6058065 (2000-05-01), Lattimore et al.
patent: 6165826 (2000-12-01), Chau et al.
patent: 6316321 (2001-11-01), Lin et al.
patent: 2001/0010961 (2001-08-01), Jung et al.

Affiliated with

Also associated with

Rating

Low bitline capacitance structure and method of making same does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Low bitline capacitance structure and method of making same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Low bitline capacitance structure and method of making same will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-2877613