Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-06-15
2002-04-16
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C700S110000, C700S120000, C700S121000, C382S144000, C382S151000
Reexamination Certificate
active
06374397
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a lot determination apparatus and method and to a recording medium for storing the lot determination method, and more particularly to a lot determination apparatus and method for determining whether or not a chip is defective by use of a pattern dimension in each process and an overlay offset, as well as to a recording medium for storing the lot determination method.
2. Description of Related Art
In a semiconductor device manufacturing process in which patterning is effected by several repetitions of photolithography, a positional relationship between an upper layer and a lower layer is very critical. If a wafer is subjected to patterning while the upper layer is greatly offset from the lower layer or while a pattern is changed greatly in size, the lot to which the wafer belongs (i.e., chips) thus patterned will not properly operate as devices. Thus, a pattern dimension inspection (hereinafter referred to as a “dimension inspection”) is indispensable for producing a conforming lot. The dimension inspection can be divided into a resist dimension inspection (hereinafter referred to as a “resist pattern inspection”) to be performed immediately after photolithography and a post-etching pattern dimension inspection (hereinafter referred to as an “etched pattern inspection”). On the basis of the interrelationships among inspection results, a determination must be made as to whether or not a wafer or chips is(are) defective, in consideration of the result of a pattern overlay inspection (hereinafter referred to as an “overlay inspection”) for checking an offset between an already-existing pattern (a first pattern) and a newly formed pattern, as well as in consideration of the foregoing inspections.
FIG. 8
shows a conventional photolithography step and a flow of inspection and determination steps following the photolithography. As illustrated in
FIG. 8
, a semiconductor manufacturing process comprises a major process A
100
, a major process B
110
, and a major process C
120
. In each of the major processes; for example, in the major process A
100
, there are performed a photolithography step
101
for newly forming a pattern on an already-existing pattern (i.e., a first pattern) through exposure and development, an overlay inspection
103
for checking an offset between the newly formed pattern and the already-existing pattern (the first pattern), a resist pattern inspection
105
for checking the dimension of a resist pattern before exfoliation, and an etched pattern inspection
109
for checking the dimension of a pattern which is formed by etching of the wafer while the resist pattern is used as a mask and by removal of the resist pattern. If a nonconforming chip is found during the overlay inspection
103
or the resist pattern inspection
105
in the course of the three steps of inspections, i.e., the overlay inspection
103
, the resist pattern inspection
105
, and the etched pattern inspection
109
, the wafer is again subjected to the photolithography step
101
. In order for conforming chips to be produced, the inspection steps mentioned above must be repeated until inspection results fall within the specifications.
FIG. 9
shows one example of an ideal photolithography pattern. In
FIG. 9
, reference numeral
6
designates a pattern (e.g., a wiring pattern) formed through a lower layer majority process A;
5
designates a pattern (e.g., holes) formed in an overlay major process B following the lower layer major process;
1
designates an etched pattern inspection target dimension (S
1
) which represents an ideal dimension to serve as the target in the lower layer major process A;
2
designates a resist pattern inspection target dimension (S
3
) which is an ideal dimension to serve as the target in the overlay major process B;
3
designates an overlay offset in the overlay major process B (S
2
, where S
2
=0, because a photolithography pattern is ideal); and
4
designates a design manual (DM) value, i.e., an allowable distance between a pattern to be imaged in the lower layer major process A and a pattern to be imaged in the overlay major process B, when patterns are imaged on the wafer in conformity with the target dimensions.
FIG. 10
shows one example of an actual photolithography pattern. In
FIG. 10
, reference numerals which are the same as those shown in
FIG. 9
designate identical elements, and hence repetition of their explanations will be omitted. In
FIG. 10
, reference numeral
7
designates the dimension (etched pattern inspection dimension R
1
) of an actually-manufactured first pattern measured in the post-etching inspection of the lower layer majority process A;
8
designates the dimension (resist pattern inspection dimension R
3
) of an actually-manufactured second pattern measured in the overlay majority process B; and
9
designates an overlay offset (R
2
) between the resist pattern inspection target dimension
2
and the dimension of the second pattern measured in the overlay major process B. As shown in
FIG. 10
, in effect, the photolithography pattern is imaged on the wafer while being offset from a target area for reasons of imprecision of a device or process employed for patterning. Therefore, to prevent production of a nonconforming wafer or chip, specifications must be determined for individual processes in expectation of worst dimensional offsets or overlay offsets for individual inspection steps. However, since the specifications are determined for individual processes in expectation of worst dimensional offsets or overlay offsets for individual inspection steps, a lot (or chips) which should essentially be deemed a conforming lot (or conforming chips) is (are) sometimes regarded to be nonconforming. As a result, the wafer is again subjected to photolithography, thereby resulting in an increase in a reprocessing ratio.
When specifications for individual processes are determined in expectation of worst dimensional offsets or overlay offsets in the manner as mentioned above, some devices cannot satisfy the required precision, with the result that carrying out a photolithography process thereon becomes impossible. For this reason, manufacturing processes are sometimes carried out under relaxation of the specifications for inspection steps. In such a case, a nonconforming lot or nonconforming chips may be overlooked, and in a subsequent step the nonconforming chips may be removed from the lot as being defective.
SUMMARY OF THE INVENTION
The object of the present invention is to solve the previously-described problem and to provide a lot determination apparatus and method which enable a reduction in the number of wafers to be re-subjected to photolithography and to prevent elimination of chips from a lot in a subsequent step, by determination of whether or not each chip is conforming, in comprehensive determination of results of a plurality of inspections such as an overlay inspection, an etched pattern inspection, and a resist pattern inspection.
According to a first aspect of the present invention, there is provided a lot determination apparatus which through inspection determines whether or not the lot of semiconductor wafers is conforming, the apparatus comprising: computational means for computing the sum of a value corresponding to a difference between the dimension of a first pattern formed on the lot and a dimension of a target pattern (or target dimension) of the first pattern, a value corresponding to a difference between a second pattern formed so as to be laid over the lot and a dimension of a target pattern (or target dimension) of the second pattern, a value corresponding to an offset between the first pattern and the second pattern when they are superimposed one on the other, and a predetermined adjustment value; and means for determining whether or not the lot is conforming, by comparison between the value obtained by the computational means and predetermined allowable value for the lot.
According to a second aspect of the present inv
Ishibashi Takeo
Miyamoto Yuki
Kik Phallaka
McDermott & Will & Emery
Mitsubishi Denki & Kabushiki Kaisha
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