Lossless co-planar wave guide in CMOS process

Details Lossless co-planar wave guide in CMOS process Lossless co-planar wave guide in CMOS process

2001-01-29

2002-10-15

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Coating of substrate containing semiconductor region or of...

Insulative material deposited upon semiconductive substrate

C438S783000, C438S787000, C438S791000

Reexamination Certificate

active

06465367

ABSTRACT:

BACKGROUND OF THE INVENTION
1.) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the fabrication of a Co-Planar Wave guide (wiring metal) in a conventional CMOS process and more particularly to Lossless Co-Planar Wave guide (CPW) in CMOS Process.
2.) Description of the Prior Art
Conventional devices have the signal lines (e.g., microwave microstrip lines) near the silicon substrate. The signal lines generate e-fields near the substrate that are a problem. Due to the Si-substrate's characteristic (loosy) to dissipate energy (from the e-fields), it is difficult to fabricate a microwave microstrip line (or signal line) in the conventional CMOS process.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,571,740 (Peterson) shows a capped microwave circuit with a standard ground plane layer.
U.S. Pat. No. 5,256,996 (Marshand et al.) shows a coplanar strip process.
U.S. Pat. No. 4,587,541 (Dalman et al.) teaches a method for a coplanar wave guide.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a Coplanar wave guide (CPW) (e.g., signal line) above the top metal layer and passivation layer.
It is an object of the present invention to provide a method for fabricating a signal line in a conventional CMOS process.
To accomplish the above objectives, the present invention provides a method of manufacturing a CMOS device where the CPW lines are formed above the top metal line and where other insulating layer are provide that reduce the e-field from the signal line to the substrate. There are four embodiments as follows.
In the first embodiment, the following layers are formed over the semiconductor structure, the passivation layer, a shielding layer (e.g., Au), a first insulator layer, a high K dielectric layer, a CPW and a second insulator layer.
In the second embodiment, no shielding layer is used and the high k dielectric layer is thicker than in the first embodiment.
In the third embodiment, a thick shielding layer is used and no high k dielectric layer.
In the fourth embodiment, the top metal layer is used as a shielding layer and no high k dielectric layer is used.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.


REFERENCES:
patent: 4587541 (1986-05-01), Dalman et al.
patent: 5256996 (1993-10-01), Marsland ey al.
patent: 5519342 (1996-05-01), McEwan
patent: 5571740 (1996-11-01), Peterson
patent: 5986517 (1999-11-01), Kobayashi et al.

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