Loop manipulation if a behavioral synthesis tool

Details Loop manipulation if a behavioral synthesis tool Loop manipulation if a behavioral synthesis tool

2008-02-28

2010-11-23

Whitmore, Stacy A (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000

Reexamination Certificate

active

07840931

ABSTRACT:
Methods and apparatus for optimizing memory accesses in a circuit design are described. According to one embodiment, a method comprises identifying a subset of variables from a multi-variable memory space that are accessed by a plurality of loops, storing the subset of variables in a separately accessible memory space, and accessing one of the stored subset of variables to recover a stored value of the one of the stored subset of variables for use by at least one of the plurality of loops during synthesis. According to another embodiment, a method comprises identifying at least a first loop and a second loop, determining whether a dependency exists between the first loop and the second loop, and merging the first loop and the second loop into a single merged loop, wherein the merging comprises mapping a plurality of memory accesses from the first loop to a sliding window.

REFERENCES:
patent: 5161221 (1992-11-01), Van Nostrand
patent: 5434969 (1995-07-01), Heilveil et al.
patent: 5502645 (1996-03-01), Guerra et al.
patent: 5526503 (1996-06-01), Kim
patent: 6064819 (2000-05-01), Franssen et al.
patent: 6064820 (2000-05-01), Subrahmanyam
patent: 6175957 (2001-01-01), Ju et al.
patent: 6609088 (2003-08-01), Wuytack et al.
patent: 6651246 (2003-11-01), Archambault et al.
patent: 6694310 (2004-02-01), Yu et al.
patent: 6745160 (2004-06-01), Ashar et al.
patent: 6952821 (2005-10-01), Schreiber
patent: 7143388 (2006-11-01), Miller et al.
patent: 7168059 (2007-01-01), Bowyer et al.
patent: 7194724 (2007-03-01), Hattori et al.
patent: 7353491 (2008-04-01), Gutberlet et al.
patent: 2001/0009032 (2001-07-01), Mohsen
patent: 2001/0034876 (2001-10-01), Panchul et al.
patent: 2003/0005404 (2003-01-01), Bowyer et al.
patent: 2003/0121010 (2003-06-01), Aubury
patent: 2003/0196181 (2003-10-01), Sano et al.
patent: 2005/0193359 (2005-09-01), Gupta et al.
patent: 2005/0283743 (2005-12-01), Mulholland et al.
patent: 2007/0006112 (2007-01-01), Gutberlet et al.
“Chapter 1: Designing with Precision C Synthesis,”Precision™C Synthesis Users and Reference Manual: Software Release 2004a, Mentor Graphics Corporation, pp. 1-1-1-21, Mar. 2004.
“Chapter 3: Design Optimization,”Precision™C Synthesis Users and Reference Manual: Software Release 2004a, Mentor Graphics Corporation, pp. 3-1-3-44, Mar. 2004.
“Parallelization and Data Transfer and Storage Optimization,” Proc. ACM conf. on Par. And Dist. Proc. Techniques and Applications, PDPTA '00, pp. 2591-2597, Las Vegas, NV, Jun. 2000.
Chiang, International Search Report for PCT/US06/22636, May 23, 2008.
Chiang, Written Opinion of the International Searching Authority for PCT/US06/22636, May 13, 2008.
Danckaert et al., “A Loop Transformation Approach for Combined Parallelization and Data Transfer and Storage Optimization,” Proc. ACM Conf. on Par. and Dist. Proc. Techniques and Applications, PDPTA '00, pp. 2591-2597, Las Vegas, NV, Jun. 2000.
Feist, “What's in a Language?”The AccelChip Accelerator, Issue 2, 3 pages, May 2004.
U.S. Appl. No. 60/285,656, filed Apr. 20, 2001, Burnette et al.
Lehtinen, “Loop Transformations and Indexing Functions,” 17 pages, http:/www.abo.fi/˜Johan.Lilius/G612/Topic2.pdf, website visited on May 25, 2004.
Tannenbaum, “Conclusions,” 1 page, http://www.cs.rpi.edu.˜tannenp/group/lcr
ode10.html, Jun. 12, 1999.
Tannenbaum, “Creation of Pipeline Loops,” 2 pages, http://www.cs.rpi.edu/˜tannenp/group/lcr
ode8.html, Jun. 12, 1999.
Tannenbaum, “Generating and Merging Well-Formed Loops,” 2 pages, http://www.cs.rpi.edu/˜tannenp/group/lcr
ode6.html, Jun. 12, 1999.
Tannenbaum, “Mercury Optimization,” 3 pages, http://www.cs.rpi.edu/˜tannenp/group/lcr
ode4.html, Jun. 12, 1999.
Tannenbaum, “Optimizing Pipelines for Target Architectures,” 2 pages, http://www.cs.rpi.edu/˜tannenp/group/lcr
ode9.html, Jun. 12, 1999.
Tannenbaum, “Parallelization,” 2 pages, http://www.cs.rpi.edu/˜tannenp/group/lcr
ode7.html, Jun. 12, 1999.
Tannenbaum, “Well-Formed Loops,” 2 pages, http://www.cs.rpi.edu/˜tannenp/group/lcr
ode5.html, Jun. 12, 1999.

Affiliated with

Also associated with

Rating

Loop manipulation if a behavioral synthesis tool does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Loop manipulation if a behavioral synthesis tool, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Loop manipulation if a behavioral synthesis tool will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-4187736