Loop latency compensated phase-locked loop

Details Loop latency compensated phase-locked loop Loop latency compensated phase-locked loop

2006-11-06

2009-12-15

Lugo, David B (Department: 2611)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C375S355000

Reexamination Certificate

active

07634040

ABSTRACT:
A loop latency compensated phase-locked loop (PLL). The loop latency compensated PLL comprises an ADC, a phase detector, a loop filter and a VCO. The ADC receives an analog input signal and an output clock to generate a digital signal. The phase detector receives the digital signal to generate an estimated phase error. The loop filter receives the estimated phase error to generate a latency compensated phase error output signal with a phase assigned by a sign-bit of the received estimated phase error. The VCO generates the output clock in response to the latency compensated phase error output signal and feeds the output clock back to the ADC.

REFERENCES:
patent: 6236343 (2001-05-01), Patapoutian
patent: 2003/0128451 (2003-07-01), Ohta et al.
patent: 2007/0028059 (2007-02-01), Gregorius
“An Improved Delay Compensation Technique for Digital Clock Recovery Loops” Fulvio Spagna, 2001; pp. 1395-1398.

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