Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Synchronizing
Reexamination Certificate
2000-11-30
2002-04-02
Le, Dinh T. (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Synchronizing
C327S553000
Reexamination Certificate
active
06366144
ABSTRACT:
PRIORITY
This application claims priority to an application entitled “Loop Filtering Apparatus for Reducing Frequency Lock-up Time and Phase Noise of a Phase Locked Loop for Use in a Future Mobile Terminal” filed in the Korean Industrial Property Office on Nov. 30, 1999 and assigned Ser. No. 99-53952, the contents of which are hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to a phase locked loop (PLL) in a mobile terminal, and in particular, to a loop filtering apparatus for reducing a frequency lock-up time and minimizing a phase noise of a PLL for use in a future mobile terminal.
2. Description of the Related Art
In general, a frequency synthesizer is used to prevent an oscillation frequency from drifting or swinging with time. Such a frequency synthesizer is typically used when generating an intermediate frequency (IF) or a carrier in a mobile terminal. A frequency generated in the PLL is fixed, and a plurality of desired frequencies are obtained by multiplying the generated frequency. A conventional frequency synthesizer is illustrated in FIG.
1
.
In the conventional frequency synthesizer, a loop filter
100
is typically implemented by a secondary or third loop filter. It is generally known that, compared with a third loop filter, a secondary loop filter has a relatively faster (or shorter) lock-up time and a poor cut-off characteristic. Therefore, it does not remove the attenuation component caused by the comparison frequency and the noise level added while passing through the PLL. In particular, when a fractional PLL is used, the secondary loop filter may not remove the fractional noise generated by the fractional order component.
In order to solve this problem, the prior art loop filter utilizes a third loop filter. Although the third loop filter may solve the foregoing problem, it has difficulty reducing the lock-up time. Particularly, since a proposed future IMT-2000 mobile terminal must support an inter-frequency hard handoff rather than the existing soft handoff, a PLL with a reduced lock-up time is required. The third loop filter, however, does not meet this requirement.
The disadvantages of the prior art loop filter will be described below with reference to an example. A conventional mobile terminal performs a handoff upon acquisition of a PN offset while searching pilot channels from the base stations in a neighbor list. However, an IMT 2000 mobile terminal performs a hard handoff by shifting to a corresponding frequency band. Therefore, for quick roaming, the mobile terminal must shift to the handoff frequency more quickly than to other frequencies. This requires the PLL to have a very short lock-up time. However, since the PLL in a conventional mobile terminal uses the third loop filter, there is a limitation on obtaining the proper phase noise and the reduced lock-up time by adjusting the loop band, due to the inherent trade-off between them. This problem is not easily solved satisfactorily, even by increasing a charge pump current to reduce the lock-up time by quick charging, and implementing the loop filter with a narrowed loop band to reduce the phase noise.
FIG. 2
shows a third loop filter
100
-
1
implemented for such a frequency synthesizer.
In conclusion, the frequency synthesizer shown in FIG.
1
and the conventional secondary loop filter implemented for this frequency synthesizer fail to reduce the lockup time and the phase noise. Therefore, the conventional frequency synthesizer is not suitable for a future IMT 2000 mobile terminal.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a PLL which is suitable for use in the future mobile terminal.
It is another object of the present invention to provide a loop filtering apparatus for a PLL, which can reduce the frequency lock-up time and minimize the phase noise.
It is yet another object of the present invention to provide a loop filtering apparatus for reducing a lock-up time and a phase noise during an operation of a PLL.
To achieve the above and other objects, a loop filtering apparatus for a phase locked loop (PLL) is provided in accordance with the present invention. The loop filtering apparatus operates as a secondary loop filter in response to a lock-up detection signal indicating a non-lock-up state in order to reduce the lock-up time, and operates as a third loop filter in response to a lock-up detection signal indicating a lock-up state in order to minimize the phase noise.
REFERENCES:
patent: 5146187 (1992-09-01), Vandegraaf
patent: 6097227 (2000-08-01), Hayashi
patent: 11103250 (1999-04-01), None
Dilworth & Barrese LLP
Le Dinh T.
Samsung Electronics Co,. Ltd.
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