Loop back device of packet communication T1 network

Details Loop back device of packet communication T1 network Loop back device of packet communication T1 network

1997-10-14

1998-12-29

Chan, Jason

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

375221, 370249, 371 205, H03D 324

Patent

active

058548165

ABSTRACT:
A loop back device of a packet communication T1 network includes: a clock generating part which inputs a frame divisional clock and a reference clock, inserts a modulated clock at a predetermined position of the reference clock to generate a main clock and is synchronous to the transformed clock position to generate a system clock for generating and extracting loop back data; a loop back data inserting part which generates the loop back data and is synchronous to the system clock generated from the clock generating part to insert the loop back data into transmission data; a framer and interface part which inputs the transmission data including the loop back data outputted from the loop back data inserting part to transmit the input data to the T1 network and receives is data from the T1 network; a loop back data extracting part which is synchronous to the system clock generated in the clock generating part to extract the loop back data from reception data outputted from the framer and interface part; and a processor which outputs the transmission data to the loop back data inserting part and inputs said loop back data extracted from said loop back data extracting part, to output network testing data.

REFERENCES:
patent: 5115451 (1992-05-01), Furlong
patent: 5274668 (1993-12-01), Marchall
patent: 5600656 (1997-02-01), Loopback
patent: 5778003 (1995-03-01), Puppa et al.
patent: 5787114 (1996-01-01), Ramamurthy et al.

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