Lookup table with relatively balanced delays

Details Lookup table with relatively balanced delays Lookup table with relatively balanced delays

2008-03-31

2008-12-30

Le, Don P (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Having details of setting or programming of interconnections...

C326S041000

Reexamination Certificate

active

07471104

ABSTRACT:
Lookup table circuits (LUTS) having multiple stages differently optimized to balance delays through the lookup table. A first multiplexing stage is optimized for a fast path from the control input to the data outputs, while a second and subsequent stage multiplexers are optimized for a fast path from data inputs to data outputs. In some embodiments, additional delay is introduced into the control inputs of the later stages, e.g., the LUT input paths with the smallest through-delays, in order to further balance the through-delays for the lookup table.

REFERENCES:
patent: 5646545 (1997-07-01), Trimberger et al.
patent: 5926036 (1999-07-01), Cliff et al.
patent: 6400180 (2002-06-01), Wittig et al.
patent: 6621298 (2003-09-01), Agrawal et al.
patent: 6667635 (2003-12-01), Pi et al.
patent: 6768335 (2004-07-01), Young et al.
patent: 6768338 (2004-07-01), Young et al.
patent: 6949951 (2005-09-01), Young et al.
patent: 6998872 (2006-02-01), Chirania et al.
patent: 7053654 (2006-05-01), Young et al.
patent: 7061271 (2006-06-01), Young et al.
patent: 7378869 (2008-05-01), Chirania et al.
patent: 7385416 (2008-06-01), Chirania et al.
Xilinx, Inc.; U.S. Appl. No. 11/725,742, filed by Kao et al. on Mar. 20, 2007.
Xilinx, Inc.; U.S. Appl. No. 11/881,504, filed by Chirania on Jul. 27, 2007.
Xilinx, Inc.; “The Programmable Logic Data Book 1994”; published 1994; available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124; pp. 2-110 thru 2-111.
Altera Corporation; “Stratix II Device Family Data Sheet”; v1.0; published Feb. 2004; available from Altera Corporation; 101 Innovation Drive, San Jose, California 95134; pp. 2-1 thru 2-22.
Krueger, Ralf et al.; WP209 (v1.0); “Virtex Variable-Input LUT Architecture”; Jan. 12, 2004; available from Xilinx, Inc.; 2100 Logic Drive, San Jose, California 95124; pp. 1-6.
Cataldo, Anthony et al.; “FPGA Vendors Revise Logic for Sub-100-nm Era”; EE Times; Feb. 2, 2004; downloaded from http://www.eetimes.com/story/OEG20040202S0019; pp. 1-4.

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