Lookahead register value tracking

Details Lookahead register value tracking Lookahead register value tracking

1999-12-29

2004-05-25

Kim, Kenneth S. (Department: 2181)

Electrical computers and digital processing systems: processing

Processing control

Arithmetic operation instruction processing

C711S213000, C711S220000, C712S208000

Reexamination Certificate

active

06742112

ABSTRACT:

FIELD OF THE INVENTION
Embodiments of the present invention relate to a register value tracker. More particularly, embodiment of the present invention relate to a register value tracker of a microprocessor.
BACKGROUND OF THE INVENTION
A known factor influencing microprocessor performance is load-to-use delay, i.e. the time required for a load instruction to fetch data from the memory hierarchy and to deliver it to the dependent instructions. With higher microprocessor frequencies, the relative performance cost of memory accesses is increased.
Techniques have been proposed to decrease the load-to-use latency. Certain techniques rely on past history of memory accesses to predict an address and perform a speculative memory request. One known technique is data prefetching. Data prefetching cuts the overall load-to-use latency by bringing likely-to-be-used data from distant memory to an upper level of the memory hierarchy ahead of time. However, data prefetching does not eliminate the load-to-use delay caused by accessing data residing in a first level data cache.
Another known technique is load-address prediction. The goal of address prediction is to speculate on the address of a load instruction during an early stage of the pipeline, and initiate the memory access earlier to hide the memory hierarchy latency. Prediction typically requires a recovery scheme in case of a misprediction, unless data delivery is performed after the address prediction is verified.
Speculative cache accesses are also known. Address generation can be sped up by speculatively performing a fast carry-free addition of the index portions of base and offset address components early in the cache access cycle. The full memory address is calculated in parallel to a speculative cache access. If the carry-free calculation of the index turns to be wrong, the cache access is re-executed. This scheme, when successful, can save one cycle of load latency.
In view of the foregoing, it can be appreciated that a substantial need exists for methods and apparatus which can advantageously track a register value to allow early resolution of a memory address.
SUMMARY OF THE INVENTION
Embodiments of the present invention include apparatus and methods to track a register value. A microprocessor can include a first register, a control circuit, and an adder. The first register can store a tracked register value. The control circuit can include an instruction input to receive at least a portion of an instruction and a first output to output an arithmetic operation indication. The adder can include a control input to receive the arithmetic operation indication, a first input to receive an immediate operand of an instruction, and a second input to receive the tracked register value.


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