Electronic digital logic circuitry – Threshold
Patent
1998-03-31
2000-02-01
Santamauro, Jon
Electronic digital logic circuitry
Threshold
326 37, 39550017, 39550018, H03K 1923
Patent
active
06020754&
ABSTRACT:
A programmable gate array is disclosed for implementing asynchronous logic. In one embodiment, the array includes a set of cells, at least one of which is programmed to function as a threshold gate having a plurality of inputs, an output, and a threshold value. Signals may assume a DATA state having a logic meaning and a NULL state that has no logic meaning. The gate output switches to NULL when all inputs are NULL, and switches to the ASSERTED state when the number of DATA inputs exceeds the threshold value. The gate preferably exhibit hysteresis such that the output remains DATA while the number of DATA inputs remains greater than zero, and less than the threshold value. In an alternate embodiment, and array of simplified threshold elements is used to form more complex threshold gates.
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Fant Karl M.
Parker David
Sobelman Gerald Edward
Santamauro Jon
Theseus Logic Inc.
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